Commits · bcfdd7861e4f390e478751c06d678066049cd061 · Lorenzo Albano / LLVM bpEVL · GitLab

Aug 07, 2017
- AMDGPU: Remove -mcpu=SI · 36b4b0be
  Matt Arsenault authored Aug 07, 2017
  36b4b0be
- AMDGPU: Remove redundant opt level check · 9d288e69
  Matt Arsenault authored Aug 07, 2017
  9d288e69
- AMDGPU: Remove FixControlFlowLiveIntervals pass · 3db45682
  Matt Arsenault authored Aug 07, 2017
  3db45682
- [InstCombine] Support (X | C1) & C2 --> (X & C2^(C1&C2)) | (C1&C2) for vector splats · 7091a743
  Craig Topper authored Aug 07, 2017
  7091a743
- AMDGPU: Use a custom areInlineCompatible · aac47c1c
  Matt Arsenault authored Aug 07, 2017
  aac47c1c
- [DebugInfo][DWARF] Address paulr's comment on rL310253. · b1b52c02
  Simon Dardis authored Aug 07, 2017
  b1b52c02
- [x86] revert r310208 to investigate test-suite failures (PR34105 / PR34097) · 807f92b8
  Sanjay Patel authored Aug 07, 2017
  807f92b8
- [DebugInfo][DWARF] Correct some usages of PRIx32 to PRIx64 · 02d9945e
  Simon Dardis authored Aug 07, 2017
  02d9945e
- [SLP] General improvements of SLP vectorization process. · 9581b425
  Alexey Bataev authored Aug 07, 2017
  9581b425
- AMDGPU: Cleanup subtarget features · 8728c5f2
  Matt Arsenault authored Aug 07, 2017
  8728c5f2
- Revert "[SLP] General improvements of SLP vectorization process." · 53d523c9
  Alexey Bataev authored Aug 07, 2017
  53d523c9
- [DAG] Extend visitSCALAR_TO_VECTOR optimization to truncated vector. · 3d3bde76
  Nirav Dave authored Aug 07, 2017
  3d3bde76
- [SLP] General improvements of SLP vectorization process. · faace8f1
  Alexey Bataev authored Aug 07, 2017
  faace8f1
- [DebugInfo][DWARF] Use PRIx64 explicitly in output. · ec4ea997
  Simon Dardis authored Aug 07, 2017
  ec4ea997
- [X86][LLVM]Expanding Supports lowerInterleavedStore() in X86InterleavedAccess (VF16 stride 4). · 680ac10a
  Michael Zuckerman authored Aug 07, 2017
  680ac10a
- [AMDGPU][MC] Corrected VOP3 version of v_interp_* instructions for VI · 50805a0b
  Dmitry Preobrazhensky authored Aug 07, 2017
  50805a0b
- [ARM] Fix assembly and disassembly for VMRS/VMSR · 7dffb9bf
  Andre Vieira authored Aug 07, 2017
  7dffb9bf
- [asan] Fix asan dynamic shadow check before copyArgsPassedByValToAllocas · 5d432ec9
  Vitaly Buka authored Aug 07, 2017
  5d432ec9
- [asan] Disable checking of arguments passed by value for --asan-force-dynamic-shadow · 629047de
  Vitaly Buka authored Aug 07, 2017
  629047de
- [SelectionDAG] reset NewNodesMustHaveLegalTypes flag between basic blocks · 5ca01695
  Guy Blank authored Aug 07, 2017
  5ca01695
- [Reassociate] Use a range loop for clarity. NFCI. · b53b075b
  Davide Italiano authored Aug 07, 2017
  b53b075b
- [Reassociate] Try to bail out early when canonicalizing. · a5cdc22e
  Davide Italiano authored Aug 07, 2017
  a5cdc22e
- [InstCombine] Remove shift handling from OptAndOp. · 576fb91a
  Craig Topper authored Aug 06, 2017
  576fb91a
- [InstCombine] Support (X ^ C1) & C2 --> (X & C2) ^ (C1&C2) for vector splats. · a1693a2e
  Craig Topper authored Aug 06, 2017
  a1693a2e
- [InstCombine] Support '(C - X) ^ signmask -> (C + signmask - X)' and '(X + C)... · 9cbdbefd
  Craig Topper authored Aug 06, 2017
  9cbdbefd
Aug 06, 2017
- [llvm-dlltool] Map the "arm64" machine type · c9263f4e
  Martin Storsjö authored Aug 06, 2017
  c9263f4e
- AMDGPU: Fix typo in feature description · a7eb14af
  Matt Arsenault authored Aug 06, 2017
  a7eb14af
- [x86] use more shift or LEA for select-of-constants · a923c2ee
  Sanjay Patel authored Aug 06, 2017
  a923c2ee
- [X86] Add comment to match closing Defs = [FPSW]. NFCI. · 17e290f1
  Simon Pilgrim authored Aug 06, 2017
  17e290f1
- [AVR] Compute code model if one is not provided · 70ab7cc5
  Meador Inge authored Aug 06, 2017
  70ab7cc5
- [InstCombine] Support ~(c-X) --> X+(-c-1) and ~(X-c) --> (-c-1)-X for splat vectors. · b5bf0160
  Craig Topper authored Aug 06, 2017
  b5bf0160
- [X86] Enable isel to use the PAUSE instruction even when SSE2 is disabled · 6bfa2aee
  Craig Topper authored Aug 05, 2017
  6bfa2aee
Aug 05, 2017
- [InstCombine] Fold (C - X) ^ signmask -> (C + signmask - X). · 9ffda5ab
  Craig Topper authored Aug 05, 2017
  9ffda5ab
- [InstCombine] Teach the code that pulls logical operators through constant... · 65dd32af
  Craig Topper authored Aug 05, 2017
  65dd32af
- [InstCombine] Support vector splats in foldSelectICmpAnd. · 1bbcab9c
  Craig Topper authored Aug 05, 2017
  1bbcab9c
- [SLPVectorizer] Add extra parameter to setInsertPointAfterBundle to handle different opcodes, NFCI. · cc2294a4
  Dinar Temirbulatov authored Aug 05, 2017
  cc2294a4
- [InstCombine] refactor trunc(binop) transforms; NFCI · 94da1de1
  Sanjay Patel authored Aug 05, 2017
  94da1de1
- [ARM] The ARM backend is MachineVerifier clean now. · d51a35e3
  Florian Hahn authored Aug 05, 2017
  d51a35e3
- [LCG] Remove yet another variable only used inside of asserts. · 691d0243
  Chandler Carruth authored Aug 05, 2017
  691d0243
- [LCG] Fold otherwise unused variable into assert. · ef42fd43
  Benjamin Kramer authored Aug 05, 2017
  ef42fd43