Commits · cd7d552e0405580ccb1700f2358e30fbd40cebfb · Lorenzo Albano / LLVM bpEVL · GitLab

Aug 31, 2017
- [AArch64] Support COFF linker directives · 865d01a3
  Martin Storsjö authored Aug 31, 2017
  865d01a3
- Temporarily revert "Update branch coalescing to be a PowerPC specific pass" · e42ac214
  Eric Christopher authored Aug 31, 2017
  e42ac214
- AMDGPU: Don't assert in TTI with fp32 denorms enabled · 376f1bd7
  Matt Arsenault authored Aug 31, 2017
  376f1bd7
- AMDGPU: Use set for tracked registers · 67e72dee
  Matt Arsenault authored Aug 31, 2017
  67e72dee
- [X86] Remove some code from fast isel that is no longer needed with i1 being an illegal type. · ead876b8
  Craig Topper authored Aug 30, 2017
  ead876b8
- [ARM] Replace fixed-size SmallSet with a bitset. · 79d53feb
  Benjamin Kramer authored Aug 30, 2017
  79d53feb
- AMDGPU: Correct operand types for v_mad_mix* · c8f8cda0
  Matt Arsenault authored Aug 30, 2017
  c8f8cda0
Aug 30, 2017
- [ARM] Use Swift error registers on non-Darwin targets · 33329764
  Brian Gesiak authored Aug 30, 2017
  33329764
- [X86] Remove unneed AVX512 check from fast isel. · f7ae101d
  Craig Topper authored Aug 30, 2017
  f7ae101d
- [WebAssembly] Add target feature for atomics · 18ba1928
  Derek Schuff authored Aug 30, 2017
  18ba1928
- [AVX512] Don't use 32-bit elements version of AND/OR/XOR/ANDN during isel... · afce0baa
  Craig Topper authored Aug 30, 2017
  afce0baa
- [GlobalISel][X86] Support variadic function call. · 36d447d8
  Igor Breger authored Aug 30, 2017
  36d447d8
- fix more typos; NFC · 7b8183fd
  Sanjay Patel authored Aug 30, 2017
  7b8183fd
- fix typos; NFC · 7e5af84c
  Sanjay Patel authored Aug 30, 2017
  7e5af84c
- [MIPS] Add support to match more patterns for BBIT instruction · 89df797e
  Strahinja Petrovic authored Aug 30, 2017
  89df797e
- [AArch64] allow v4f16 types when FullFP16 is supported · be5b60f7
  Sjoerd Meijer authored Aug 30, 2017
  be5b60f7
- [AVX512] Correct isel patterns to support selecting masked vbroadcastf32x2/vbroadcasti32x2 · 17854ecf
  Craig Topper authored Aug 30, 2017
  17854ecf
- [AVX512] Use 256-bit extract instructions for extracting bits [255:128] from a 512-bit register · 48a79170
  Craig Topper authored Aug 30, 2017
  48a79170
- [X86] Apply SlowIncDec feature to Sandybridge/Ivybridge CPUs as well · ef1f7166
  Craig Topper authored Aug 30, 2017
  ef1f7166
- [X86] Provide a separate feature bit for macro fusion support instead of basing it on the AVX flag · 641e2af9
  Craig Topper authored Aug 30, 2017
  641e2af9
- AMDGPU: Don't look for DS merge candidates with one use address · 3cb61634
  Matt Arsenault authored Aug 30, 2017
  3cb61634
- [AMDGPU] Use v_max_f* for fcanonicalize · 06cab79e
  Stanislav Mekhanoshin authored Aug 30, 2017
  06cab79e
- AMDGPU: Select clamp pattern with v2f16 · 6b114d2c
  Matt Arsenault authored Aug 30, 2017
  6b114d2c
- [X86] Finish the subtarget and predicate implementation of CLWB. · 559f61e1
  Craig Topper authored Aug 29, 2017
  559f61e1
Aug 29, 2017
- AMDGPU: Fix typo · 2d69c924
  Matt Arsenault authored Aug 29, 2017
  2d69c924
- [X86] Fix copy pasto from r311841. Call getOnesVector instead of getZeroVector. · a54ca1a6
  Craig Topper authored Aug 29, 2017
  a54ca1a6
- [ARM] - Tidy-up ARMAsmPrinter.cpp · 5766b8ee
  Javed Absar authored Aug 29, 2017
  5766b8ee
- [ARM] GlobalISel: Select globals in PIC mode · c9f29c62
  Diana Picus authored Aug 29, 2017
  c9f29c62
- Revert "The current version of LLVM X86 disassembler incorrectly interprets... · 5bea5240
  Eric Christopher authored Aug 29, 2017
  5bea5240
- Mark Knights Landing as having slow two memory operand instructions · 62c47a2a
  Craig Topper authored Aug 29, 2017
  62c47a2a
- [AArch64] Adjust the cost model for Exynos M1 and M2 · 4976d6a0
  Evandro Menezes authored Aug 28, 2017
  4976d6a0
- [AArch64] Adjust the cost model for Exynos M1 and M2 · 509516d2
  Evandro Menezes authored Aug 28, 2017
  509516d2
Aug 28, 2017
- [AArch64][Falkor] Avoid generating STRQro* instructions · 40cdc0e0
  Geoff Berry authored Aug 28, 2017
  40cdc0e0
- Fix ARMv4 support · 0f76a35c
  Joerg Sonnenberger authored Aug 28, 2017
  0f76a35c
- [ARM] Fix bug in ARMLoadStoreOptimizer when kill flags are missing. · 75c4ae30
  Geoff Berry authored Aug 28, 2017
  75c4ae30
- [Power9] Add new instructions for floating point status and control registers. · c35e4de3
  Stefan Pintilie authored Aug 28, 2017
  c35e4de3
- [Hexagon] Check for potential bank conflicts in post-RA scheduling · 2164a271
  Krzysztof Parzyszek authored Aug 28, 2017
  2164a271
- [AMDGPU] Fix regression in AMDGPULibCalls allowing native for doubles · 312c557b
  Stanislav Mekhanoshin authored Aug 28, 2017
  312c557b
- [AMDGPU] computeKnownBitsForTargetNode for 24 bit mul · dad7cf62
  Stanislav Mekhanoshin authored Aug 28, 2017
  dad7cf62
- [Hexagon] Break up DAG mutations into separate classes, move to subtarget · 95da97ec
  Krzysztof Parzyszek authored Aug 28, 2017
  95da97ec