Commits · d056d5decfb593cfc53b421a89075d2063f76ec9 · Lorenzo Albano / LLVM bpEVL · GitLab

Feb 19, 2021
- [RISCV] Use custom isel for vector indexed load/store intrinsics. · d056d5de
  Craig Topper authored Feb 19, 2021
  d056d5de
- [RISCV] Prevent selecting a 0 VL to X0 for the segment load/store intrinsics. · dbf910f0
  Craig Topper authored Feb 19, 2021
  dbf910f0
- [RISCV] Move SHFLI matching to DAG combine. Add 32-bit support for RV64 · 98dff5e8
  Craig Topper authored Feb 19, 2021
  98dff5e8
- [RISCV] Address some clang-tidy warnings. NFCI. · d9531a30
  Fraser Cormack authored Feb 19, 2021
  
  d9531a30
- [RISCV] Prune unneeded indexed load/store pseudo instructions. · cd4051ac
  Craig Topper authored Feb 18, 2021
  cd4051ac
- [RISCV] Split zvlsseg searchable table into 4 separate tables. Index by... · 8ed3bbbc
  Craig Topper authored Feb 18, 2021
  8ed3bbbc
- [RISCV] Enable PrimaryKeyEarlyOut on RISCVVPseudosTable. · cf345591
  Craig Topper authored Feb 18, 2021
  cf345591
Feb 18, 2021
- [RISCV] Simplify VPseudoAMOEI multiclass. NFC · 0db93831
  Craig Topper authored Feb 18, 2021
  0db93831
- [RISCV] Use XLenRI alias for RegInfoByHwMode instances · 74df1ffa
  Jessica Clarke authored Feb 13, 2021
  74df1ffa
- [RISCV] Add support for fixed vector MULHU/MULHS. · 156fc07e
  Craig Topper authored Feb 18, 2021
  156fc07e
- [RISCV] Add support for fixed vector sign/zero extend from mask types. · 792627be
  Craig Topper authored Feb 18, 2021
  792627be
- [RISCV] Support isel of scalable vector bitcasts · c7dd92e8
  Craig Topper authored Feb 18, 2021
  c7dd92e8
- [RISCV] Fix typo. Use ValueType instead of LLVMType. · 065a187f
  Hsiangkai Wang authored Feb 18, 2021
  
  065a187f
- [RISCV] Fix bugs in pseudo instructions for masked segment load. · f1efa8ab
  Hsiangkai Wang authored Feb 18, 2021
  f1efa8ab
- [NFC][RISCV] Use concise way to describe load/store instructions. · b97d8b32
  Hsiangkai Wang authored Feb 18, 2021
  b97d8b32
- [RISCV] Rewrite assert to not give unused variable warnings in Release builds · ae1e6c35
  Benjamin Kramer authored Feb 18, 2021
  ae1e6c35
- [RISCV] Begin to support more subvector inserts/extracts · d8762149
  Fraser Cormack authored Feb 17, 2021
  d8762149
- [RISCV] Guard LowerINSERT_VECTOR_ELT against fixed vectors. · 016eca8f
  Craig Topper authored Feb 17, 2021
  016eca8f
- [RISCV] Guard the ISD::EXTRACT_VECTOR_ELT handling in ReplaceNodeResults... · 00c4e0a8
  Craig Topper authored Feb 17, 2021
  00c4e0a8
Feb 17, 2021
- [RISCV] Localize RISCVZvlssegTable to RISCVISelDAGToDAG.cpp, the only place it is used. · 3bdd0273
  Craig Topper authored Feb 17, 2021
  
  3bdd0273
- [RISCV] Use bits<7> instead of bits<11> for the EEW field size in the... · 799f7865
  Craig Topper authored Feb 17, 2021
  799f7865
- [RISCV] Merge the handlers for masked and unmasked segment loads/stores. · d4353a31
  Craig Topper authored Feb 16, 2021
  d4353a31
- [RISCV] Merge the vsetvli and vsetvlimax intrinsic selection · 6f30d003
  Craig Topper authored Feb 16, 2021
  6f30d003
- [RISCV] Simplify BP initialisation · 709ea8bc
  luxufan authored Feb 17, 2021
  709ea8bc
- [RISCV] Add support for fixed vector vselect · d8116164
  Fraser Cormack authored Feb 15, 2021
  d8116164
- [RISCV] Spilling for RISC-V V extension. (2nd version) · a3c783db
  Hsiangkai Wang authored Jan 08, 2021
  a3c783db
- [RISCV] Frame handling for RISC-V V extension. · 5a31a673
  Hsiangkai Wang authored Jan 08, 2021
  5a31a673
Feb 16, 2021
- [RISCV] Add isel patterns for fixed vector fmsub/fnmadd/fnmsub. · 61a238e6
  Craig Topper authored Feb 16, 2021
  
  61a238e6
- [RISCV] Add support for fixed vector mask logic operations. · 07ca13fe
  Craig Topper authored Feb 16, 2021
  07ca13fe
- [RISCV] Fix a crash in fixed-length build_vector lowering · 04977ce5
  Fraser Cormack authored Feb 15, 2021
  04977ce5
- [RISCV] Add patterns for scalable-vector fabs & fcopysign · b8701990
  Fraser Cormack authored Feb 04, 2021
  b8701990
Feb 15, 2021
- [RISCV] Add expicit i32/i64 types to RV32 or RV64 only isel patterns. NFC · 29b894a8
  Craig Topper authored Feb 15, 2021
  29b894a8
- [RISCV] Add support for fixed vector floating point setcc. · 7ba2e1c6
  Craig Topper authored Feb 15, 2021
  7ba2e1c6
- [RISCV] Convert VSLIDE(UP|DOWN) nodes to "VL" versions (NFC) · 4bd5bd40
  Fraser Cormack authored Feb 11, 2021
  4bd5bd40
Feb 13, 2021
- [RISCV] Rename the RVVBaseAddr ComplexPattern to just BaseAddr and use it to... · 3520371d
  Craig Topper authored Feb 13, 2021
  3520371d
- [RISCV] Move riscv_vfmv_v_f_vl patterns to RISCVInstrInfoVVLPatterns.td for... · 532d4bf0
  Craig Topper authored Feb 12, 2021
  532d4bf0
- [RISCV] Add support for fixed vector fabs · 4220a81c
  Craig Topper authored Feb 12, 2021
  
  4220a81c
- [RISCV] Add support for fixed vector sqrt. · 36658376
  Craig Topper authored Feb 12, 2021
  
  36658376
Feb 12, 2021
- [RISCV] Use a ComplexPattern to merge the PatFrags for removing unneeded masks on shift amounts. · d32ed9b2
  Craig Topper authored Feb 12, 2021
  d32ed9b2
- [RISCV] Add support for integer fixed vector setcc · 1697cc78
  Craig Topper authored Feb 12, 2021
  1697cc78