llvm-svn: 27555

llvm-svn: 27554

letting the code generator handle them directly.

llvm-svn: 27539

llvm-svn: 27506

llvm-svn: 27501

llvm-svn: 27497

llvm-svn: 27496

entry point of a function.

llvm-svn: 27494

llvm-svn: 27491

Also MOVPDI2DIrr.

llvm-svn: 27476

- Normalize shuffle nodes so result vector lower half elements come from the
  first vector, the rest come from the second vector. (Except for the
  exceptions :-).
- Other minor fixes.

llvm-svn: 27474

llvm-svn: 27473

llvm-svn: 27446

llvm-svn: 27445

llvm-svn: 27444

vector_shuffle v1, v1, <0, 4, 1, 5, 2, 6, 3, 7>

This is turned into
vector_shuffle v1, <undef>, <0, 0, 1, 1, 2, 2, 3, 3>
by dag combiner.

It would match a {p}unpckl on x86.

llvm-svn: 27437

llvm-svn: 27434

llvm-svn: 27433

llvm-svn: 27427

llvm-svn: 27412

llvm-svn: 27410

llvm-svn: 27405

llvm-svn: 27393

llvm-svn: 27388

llvm-svn: 27384

Use movhpd to: store upper f64 extracted from v2f64.

llvm-svn: 27382

- Some bug fixes and naming inconsistency fixes.

llvm-svn: 27377

INSERT_VECTOR_ELT to insert a 16-bit value in a 128-bit vector.

llvm-svn: 27314

llvm-svn: 27310

from a 128-bit vector.

llvm-svn: 27304

llvm-svn: 27275

llvm-svn: 27272

llvm-svn: 27271

Use pshufd, pshuhw, and pshulw to shuffle v4f32 if shufps doesn't match.
Use shufps to shuffle v4f32 if pshufd, pshuhw, and pshulw don't match.

llvm-svn: 27259

llvm-svn: 27257

llvm-svn: 27256

llvm-svn: 27255

For example, packsswb actually creates a v16i8 from a pair of v8i16. But since
the intrinsic specification forces the output type to match the operands.

llvm-svn: 27254

- Added SSE2 128-bit integer pack with signed saturation ops.
- Added pshufhw and pshuflw ops.

llvm-svn: 27252

vector_shuffle undef.

llvm-svn: 27250