comment in the generated table.

llvm-svn: 99794

where an incorrect number of operands is provided to an sdnode instead
of just a few cases.

llvm-svn: 99761

and those derived from them.  These are obnoxious because
they were written as: PatLeaf<(bitconvert).  Not having an
argument was foiling adding better type checking for operand
count matching up with what was required (in this case,
bitconvert always requires an operand!)

llvm-svn: 99759

transforming it into (add (i32 GPR), 4).  This allows us to write type
generic multi patterns and have tblgen automatically drop the bitconvert
in the case when the types align.  This allows us to fold an extra load
in the changed testcase.

llvm-svn: 99756

llvm-svn: 99747

by rotating it.

llvm-svn: 99746

llvm-svn: 99744

1, 1 cases which are by-far the most frequent.  This shrinks the X86
isel table from 77014 -> 74657 bytes.

llvm-svn: 99740

issues to get here.  We now trim the result type list of the
CompleteMatch or MorphNodeTo operation to be the same size as the
thing we're matching.  this means that if you match (add GPR, GPR)
with an instruction that produces a normal result and a flag that
we now trim the result in tblgen instead of having to do it 
dynamically.  This exposed a bunch of inconsistencies in result
counting that happened to be getting lucky since the days of the
old isel.

llvm-svn: 99728

same vt multiple times for a register.  For example,
ECX is in 5 different i32 reg classes, just return 
1 i32 instead of 5.

llvm-svn: 99727

from two places in CodeGenDAGPatterns.cpp, and
use it in DAGISelMatcherGen.cpp instead of using
an incorrect predicate that happened to get lucky
on our current targets.

llvm-svn: 99726

results forward.  We can now handle an instruction that 
produces one implicit def and one result instead of one or
the other when not at the root of the pattern.

llvm-svn: 99725

the index comments nested under OPC_SwitchOpcode were off by one.
This fixes the comments.

llvm-svn: 99722

llvm-svn: 99714

llvm-svn: 99703

Remove much horribleness from X86InstrFormats as a result. Similar
simplifications are probably possible for other targets.

llvm-svn: 99539

bytes instead of one byte.  This is important because
we're running up to too many opcodes to fit in a byte
and it is aggrevated by FIRST_TARGET_MEMORY_OPCODE
making the numbering sparse.  This just bites the
bullet and bloats out the table.  In practice, this
increases the size of the x86 isel table from 74.5K
to 76K.  I think we'll cope :)

This fixes rdar://7791648

llvm-svn: 99494

If a TableGen class has an initializer expression containing an X.Y subexpression,
AND X depends on template parameters,
AND those template parameters have defaults,
AND some parameters with defaults are beyond position 1,
THEN parts of the initializer expression are evaluated prematurely with the default values when the first explicit template parameter is substituted, before the remaining explicit template parameters have been substituted.

llvm-svn: 99492

in some more places.

llvm-svn: 99366

instead of reimplementing it wrong and poorly.

llvm-svn: 99357

llvm-svn: 99354

llvm-svn: 99353

llvm-svn: 99347

instead of as a single element list with VoidTy.  Now with a fix
for the verifier.

llvm-svn: 99206

llvm-svn: 99111

llvm-svn: 99011

instead of as a single element list with VoidTy.

llvm-svn: 99009

ApplyTypeConstraint) and make it handle multiple result nodes.

llvm-svn: 99003

to maintain a list of types (one for each result of
the node) instead of a single type.  There are liberal
hacks added to emulate the old behavior in various
situations, but they can start disolving now.

llvm-svn: 98999

we don't blow the smallvector as often.  No functionality change.

llvm-svn: 98968

from the pattern if present, and we use it instead of the bit.

llvm-svn: 98938

dag isel gen instead of instruction properties.  This
allows the oh-so-useful behavior of matching a variadic
non-root node.

llvm-svn: 98934

llvm-svn: 98933

llvm-svn: 98927

llvm-svn: 98918

record* -> instrinfo instead of std::string -> instrinfo.

This speeds up tblgen on cellcpu from 7.28 -> 5.98s with a debug
build (20%).

llvm-svn: 98916

Use CodeGenTarget::getInstNamespace in one place and fix it.

llvm-svn: 98915

llvm-svn: 98914

llvm-svn: 98912

to a vector that CGT stores instead of synthesizing it on every 
call.

llvm-svn: 98910