llvm-svn: 103327

llvm-svn: 103325

and not the real problem itself, by dropping debug info for i128 values.
rdar://7958162.

llvm-svn: 103310

llvm-svn: 103305

llvm-svn: 103304

llvm-svn: 103303

getConstantFP to accept the two supported long double
target types.  This was not the original intent, but
there are other places that assume this works and it's
easy enough to do.

llvm-svn: 103299

llvm-svn: 103295

llvm-svn: 103272

patch by Peter Housel!

llvm-svn: 103267

llvm-svn: 103233

lowered copies.

llvm-svn: 103228

llvm-svn: 103227

increase in the debug line info section, and it's causing
regressions in a gdb testsuite.

llvm-svn: 103226

doesn't have to guess.

llvm-svn: 103194

llvm-svn: 103193

llvm-svn: 103185

with the fix in 103157.

%reg1039:1<def> = VMOVS %S1<kill>, pred:14, pred:%reg0
is not coalescable since none of the super-registers of S1 are in reg1039's
register class: DPR_VFP2. But it is still a legal copy instruction so it should
not assert.

llvm-svn: 103170

llvm-svn: 103145

Users can write broken code that emits the same label twice with asm renaming,
detect this and emit a fatal backend error instead of aborting.

llvm-svn: 103140

llvm-svn: 103139

support a new bottom-up mode.

llvm-svn: 103138

of just letting them inherit the debug locations of adjacent instructions.

Debug info should aim to be either accurate or absent.

llvm-svn: 103135

llvm-svn: 103133

llvm-svn: 103126

llvm-svn: 103109

Teach liveintervalanalysis about virtual registers which are defined by reg_sequence instructions that are formed by registers defined by distinct instructions. e.g.
80      %reg1041:6<def> = VSHRNv4i16 %reg1034<kill>, 12, pred:14, pred:%reg0
. . .
120     %reg1041:5<def> = VSHRNv4i16 %reg1039<kill>, 12, pred:14, pred:%reg0

llvm-svn: 103102

MachineSSAUpdater to avoid duplicating all the code.

llvm-svn: 103060

Teach PHI elimination to remove REG_SEQUENCE instructions and update references of the source operands with references of the destination with subreg indices. e.g.
%reg1029<def>, %reg1030<def> = VLD1q16 %reg1024<kill>, ...
%reg1031<def> = REG_SEQUENCE %reg1029<kill>, 5, %reg1030<kill>, 6
=>
%reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...

PHI elimination now does more than phi elimination. It is really a de-SSA pass.

llvm-svn: 103039

llvm-svn: 103013

llvm-svn: 103001

Instruction selection optimizations may have moved the def of a function argument out of the entry block. rdar://7937489

llvm-svn: 102993

llvm-svn: 102984

llvm-svn: 102981

This should make it possible to start producing kill flags in isel without
breaking stuff.

llvm-svn: 102976

in registers into a separate function to de-couple it from the
top-down-specific logic in getRegForValue.

llvm-svn: 102975

This fixes PR6941.

llvm-svn: 102970

llvm-svn: 102966

debug output is showing machine instructions, the IR-level basic block names
aren't very meaningful, and because multiple machine basic blocks may be
derived from one IR-level BB, they're also not unique.

llvm-svn: 102960

beneficial cases. See the changes in test/CodeGen/X86/tail-opts.ll and
test/CodeGen/ARM/ifcvt2.ll for details.

The fix is to change HashEndOfMBB to hash at most one instruction,
instead of trying to apply heuristics about when it will be profitable to
consider more than one instruction. The regular tail-merging heuristics
are already prepared to handle the same cases, and they're more precise.

Also, make test/CodeGen/ARM/ifcvt5.ll and
test/CodeGen/Thumb2/thumb2-branch.ll slightly more complex so that they
continue to test what they're intended to test.

And, this eliminates the problem in
test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll, the testcase from
PR5204. Update it accordingly.

llvm-svn: 102907