dylib. This regressed with r145408. I will try to make a test case and add it
so that this doesn't happen again.

llvm-svn: 149667

llvm-svn: 149655

PHI nodes which were matched, rather than climbing up the
original PHI node's operands to rediscover PHI nodes for
recording, since the PHI nodes found that are not
necessarily part of the matched set.
This fixes rdar://10589171.

llvm-svn: 149654

that just uses the new toolchain probing logic. This fixes linking with -m32 on
64 bit systems (the /32 dir was not being added to the search).

llvm-svn: 149651

llvm-svn: 149650

llvm-svn: 149649

More targetted fix replacing d0e277d272d517ca1cda368267d199f0da7cad95.

llvm-svn: 149648

This reverts commit d0e277d272d517ca1cda368267d199f0da7cad95.

llvm-svn: 149647

It doesn't seem worthwhile to give meaning to a NULL register mask
pointer. It complicates all the code using register mask operands.

llvm-svn: 149646

llvm-svn: 149643

build/Make: Add missing dependency, LLVMBuild makefile fragment implicitly depends on Makefile.config.

llvm-svn: 149642

NEON loads and stores accept single and double spaced pairs, triples,
and quads of D registers.  This patch adds new register classes to
accurately model those constraints:

  Dn, Dn+1    Dn, Dn+2
  ----------------------
  DPair       DPairSpc
  DTriple     DTripleSpc
  DQuad       DQuadSpc

Also extend the existing QQ and QQQQ register classes to contains all Q
pairs and quads instead of just the aligned ones.

These new register classes will make it possible to accurately model
constraints on NEON loads and stores, and we can get rid of all the NEON
pseudo-instructions.  The late scheduler will be able to accurately
model instruction dependencies from the explicit operands.

This more than doubles the number of ARM registers, but the backend
passes are quite good at handling this. The llc -O0 compile time only
regresses by 1.5%.  Future work on register mask operands will recover
this regression.

llvm-svn: 149640

llvm-svn: 149615

Also silences warnings about bodyless for loops.

llvm-svn: 149612

As suggested by Nick Lewycky, the tree traversal queues have been changed to SmallVectors and the associated loops have been rotated. Also, an 80-col violation was fixed.

llvm-svn: 149607

Move test/CodeGen/Generic/2012-02-01-CoalescerBug.ll to CodeGen/ARM, for now. It requires TARGETS=arm.

I cannot reproduce a fixed issue with other targets.

llvm-svn: 149604

llvm-svn: 149601

Special handling was added for v4i32 -> v4i64 and v8i16 -> v8i32
extensions.

llvm-svn: 149600

llvm-svn: 149599

Re-apply the coalescer fix from r149147. Commit r149597 should have fixed the llvm-gcc and clang self-host issues.

llvm-svn: 149598

llvm-svn: 149597

llvm-svn: 149596

Long basic blocks with many candidate pairs (such as in the SHA implementation in Perl 5.14; thanks to Roman Divacky for the example) used to take an unacceptably-long time to compile. Instead, break long blocks into groups so that no group has too many candidate pairs.

llvm-svn: 149595

more than two adjacent ranges needed to be merged. The new version should be
able to handle an arbitrary sequence of adjancent ranges.

llvm-svn: 149588

 

llvm-svn: 149585

selector registers.
 

llvm-svn: 149584

 

llvm-svn: 149583

llvm-svn: 149576

This was the cause of the silent failure to generate
clang's config.h. My bad.

Fix on r149563 / r149568.

llvm-svn: 149574

llvm-svn: 149569

Keep the string empty when unspecified. Undoes
part of r149563.

llvm-svn: 149568

llvm-svn: 149567

configure was silently failing to produce anything in the case
where clang wasn't at tools/clang/, resulting in compilation
errors much later in the build when config.h didn't exist.

llvm-svn: 149563

llvm-svn: 149562

llvm-svn: 149561

Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.

Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.

Adds a test to verify that the scheduler is working.

Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.

Patch by Preston Gurd!

llvm-svn: 149558

llvm-svn: 149557

It is simpler to define a composite index directly:

  def ssub_2 : SubRegIndex<[dsub_1, ssub_0]>;
  def ssub_3 : SubRegIndex<[dsub_1, ssub_1]>;

Than specifying the composite indices on each register:

  CompositeIndices = [(ssub_2 dsub_1, ssub_0),
                      (ssub_3 dsub_1, ssub_1)] in ...

This also makes it clear that SubRegIndex composition is supposed to be
unique.

llvm-svn: 149556

llvm-svn: 149553

The final tie breaker comparison also needs to return +/-1, or 0.
This is not a less() function.

This could cause otherwise identical super-classes to be ordered
unstably, depending on what the system qsort routine does with a bad
compare function.

llvm-svn: 149549