llvm-svn: 41344

llvm-svn: 41238

llvm-svn: 41236

llvm-svn: 41235

llvm-svn: 41234

llvm-svn: 41233

llvm-svn: 41231

llvm-svn: 41226

llvm-svn: 41215

llvm-svn: 41202

llvm-svn: 41188

to getBase and getIdx.  getBase and getIdx now return a "normalized" view
of the expression (e.g., always "A[4]" instead of possibly "4[A]").  getLHS
and getRHS return the expressions with syntactic fidelity to the original
source code.

Also modified client code of ArraySubscriptExpr, including the AST dumper
and pretty printer, the return-stack value checker, and the LLVM code
generator.

llvm-svn: 41180

aggregate value and scalar expression computation are very different, this
gets them away from each other.  This causes a temporary regression on some
complex number examples.

llvm-svn: 41014

llvm-svn: 40995

codegen for:

_Complex double bar(int);
void test(_Complex double*);

void test2(int c) {
  _Complex double X;
  X = bar(1);
  test(&X);
}

llvm-svn: 40993

bitcast.

llvm-svn: 40992

EmitUsualArithmeticConversions.

llvm-svn: 40931

EmitExprWithUsualUnaryConversions.

llvm-svn: 40929

struct X { int A; };

void foo() {
  struct X s;
  int i;
  i = __builtin_choose_expr(0, s, i);
}

compiles to:

        %tmp = load i32* %i             ; <i32> [#uses=1]
        store i32 %tmp, i32* %i

wow :)

llvm-svn: 40801

llvm-svn: 40788

Rename AddrLabel and OCUVectorComponent -> AddrLabelExpr and OCUVectorElementExpr respectively.  This is for consistency with other expr nodes end with *Expr.

llvm-svn: 40785

   vec2.yx = vec2; // reverse
 

llvm-svn: 40782

    vec2.x = f;

llvm-svn: 40781

llvm-svn: 40780

llvm vector shuffle instead of a bunch of insert/extract operations.
For:   vec4 = vec4.yyyy;  // splat

Emit:
        %tmp1 = shufflevector <4 x float> %tmp, <4 x float> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > 

instead of:

        %tmp1 = extractelement <4 x float> %tmp, i32 1          
        %tmp2 = insertelement <4 x float> undef, float %tmp1, i32 0             
        %tmp3 = extractelement <4 x float> %tmp, i32 1          
        %tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 1             
        %tmp5 = extractelement <4 x float> %tmp, i32 1          
        %tmp6 = insertelement <4 x float> %tmp4, float %tmp5, i32 2             
        %tmp7 = extractelement <4 x float> %tmp, i32 1          
        %tmp8 = insertelement <4 x float> %tmp6, float %tmp7, i32 3             

llvm-svn: 40779

llvm-svn: 40777

like this:

typedef __attribute__(( ocu_vector_type(4) )) float float4;
float4 test1(float4 V) {
  return V.wzyx+V;
}

to:
_test1:
        pshufd  $27, %xmm0, %xmm1
        addps   %xmm0, %xmm1
        movaps  %xmm1, %xmm0
        ret

and:

_test1:
        mfspr r2, 256
        oris r3, r2, 4096
        mtspr 256, r3
        li r3, lo16(LCPI1_0)
        lis r4, ha16(LCPI1_0)
        lvx v3, r4, r3
        vperm v3, v2, v2, v3
        vaddfp v2, v3, v2
        mtspr 256, r2
        blr 

llvm-svn: 40771

We can now codegen:

  vec4.xy;

as nothing!

llvm-svn: 40769

llvm-svn: 40665

llvm-svn: 40162

llvm-svn: 40009

codegen to compile:

int test(int *A, int *B) {
  return A-B;
}

into:

_test:
        movl 4(%esp), %eax
        subl 8(%esp), %eax
        sarl $2, %eax
        ret

instead of:

_test:
        movl 4(%esp), %eax
        subl 8(%esp), %eax
        movl %eax, %ecx
        sarl $31, %ecx
        shrl $30, %ecx
        addl %ecx, %eax
        sarl $2, %eax
        ret

llvm-svn: 39902

llvm-svn: 39884

llvm-svn: 39858

compute type alignment.  This info is needed for struct layout.

llvm-svn: 39850

llvm-svn: 39847

llvm-svn: 39841

where ASTContext can manage caches for struct layout, etc.

llvm-svn: 39835

llvm-svn: 39831

Both in one patch, and the test case that Chris didn't commit last
time is in there too...

I'll split the patch up if somebody wants it split."

Patch by Keith Bauer.

llvm-svn: 39796