are, simplify logic, and cause things to not be nested as deeply.  This also
uses MRI->areAliases instead of an explicit loop.

No functionality change, just code cleanup.

llvm-svn: 23296

as setcc and select next.

llvm-svn: 23295

llvm-svn: 23294

only add a reload live range once for the instruction.  This is one step
towards fixing a regalloc pessimization that Nate notice, but is later undone
by the spiller (so no code is changed).

llvm-svn: 23293

is zero.  This lets the register allocator elide some copies in some cases.

This implements CodeGen/PowerPC/rlwimi-commute.ll

llvm-svn: 23292

1. Add support for defining Pattern's, which can match expressions when there
   is no instruction that directly implements something.  Instructions usually
   implicitly define patterns.
2. Add support for defining SDNodeXForm's, which are node transformations.
   This seperates the concept of a node xform out from the existing predicate
   support.

Using this new stuff, we add a few instruction patterns, one for testing, and
two for OR/XOR by an arbitrary immediate.

llvm-svn: 23286

llvm-svn: 23283

llvm-svn: 23278

the rest of the instructions, add comment markers to seperate portions of
the file into logical parts

llvm-svn: 23277

llvm-svn: 23268

for matching signed 16-bit and shifted 16-bit ppc immediates

llvm-svn: 23267

llvm-svn: 23266

llvm-svn: 23263

llvm-svn: 23262

as well as fixing how we replace old values with new values.

llvm-svn: 23260

preserve livevar

llvm-svn: 23259

This restores all of stanford to being identical with and without the dag
combiner with the add folding turned off in sd.cpp.

llvm-svn: 23258

'' is not a recognized processor for this target (ignoring processor)

Default to "generic" instead of "" for the default CPU.

llvm-svn: 23257

'' is not a recognized processor for this target (ignoring processor)

instead of:

 is not a recognized processor for this target (ignoring processor)

llvm-svn: 23256

we were losing a node, causing an assertion to fail.  Now we eagerly delete
discovered CSE's, and provide an optional vector to keep track of these
discovered equivalences.

llvm-svn: 23255

that option for PowerPC's beta.

llvm-svn: 23253

are allowed to generate 64-bit-only PowerPC instructions for 32 bit hosts,
such as the PowerPC 970.

This speeds up 189.lucas from 81.99 to 32.64 seconds.

llvm-svn: 23250

llvm-svn: 23246

llvm-svn: 23245

generate the fun in-register fp<->long instructions.

llvm-svn: 23244

I have run so far when run before Legalize.  It still needs to pick up the
SetCC folds, and nodes that use SetCC.

llvm-svn: 23243

llvm-svn: 23241

llvm-svn: 23240

llvm-svn: 23239

llvm-svn: 23238

llvm-svn: 23235

switch should never be exited, so its bottom is now unreachable.

llvm-svn: 23234

Define the PatFrag class which can be used to define subpatterns to match
things with.  Define 'not', and use it to define the patterns for andc,
nand, etc.

llvm-svn: 23233

llvm-svn: 23232

values, and then we should be able to hook it up.

llvm-svn: 23231

currently don't do anything.  This elides patterns for binary operators
that ping on the carry flag, since we don't model it yet.

This patch also removes PPC::SUB, because it is dead.

llvm-svn: 23230

llvm-svn: 23229

i64 values on targets that need that expanded to 32-bit registers.  This fixes
PowerPC/2005-09-02-LegalizeDuplicatesCalls.ll and speeds up 189.lucas from
taking 122.72s to 81.96s on my desktop.

llvm-svn: 23228

llvm-svn: 23226

llvm-svn: 23224