llvm-svn: 40123

code that cross integer / floating point domains (e.g. generate pxor / pand for
logical ops on floating point value, movdqa to load / store floating point SSE
values). Given that, it's better to use movaps instead of movdqa and movups
instead of movdqu. They have the same latency but the "aps" variants are one
byte shorter.
If the domain crossing problem is a real performance issue, then we will have to
fix it with dynamic programming based isel.

llvm-svn: 40076

llvm-svn: 40074

llvm-svn: 40071

Fix patterns so we isel the xorps, etc. for floating pt logical SSE ops. DAG combiner may fold away the (bit_convert (load)).

llvm-svn: 40070

InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033

llvm-svn: 40030

llvm-svn: 40028

Use MOV instead of LEA to restore ESP if callee-saved frame size is 0; if previous instruction updates esp, fold it in.

llvm-svn: 40018

and stores that have a specified alignment of less than 16 bytes now use
instructions that support misaligned memory references.

llvm-svn: 40015

llvm-svn: 39998

llvm-svn: 39984

llvm-svn: 39978

llvm-svn: 39977

Missed the case where alloca is used but the stack size (not including callee-saved portion) is zero. Thanks Dan.

llvm-svn: 39974

llvm-svn: 39967

llvm-svn: 39962

llvm-svn: 39921

This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.

In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.

After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be 
thought as 'finished': I expect many small and not so small glitches
everywhere.

llvm-svn: 39855

llvm-svn: 39843

Change name of -sched option and DEBUG_TYPE to
pre-RA-sched; adjust testcases.

llvm-svn: 39816

llvm-svn: 39813

following jump tables that it earlier inserted.  This
would be OK on other targets but is needed for correctness
only on ARM (constant islands needs to find jump tables).

llvm-svn: 39782

llvm-svn: 39772

Fixed print immediate 
Fixed Identation on MipsISelDAGToDAG.cpp

llvm-svn: 39764

Prologue/Epilogue support fp,ra save/restore and use the stack frame the right
way!

llvm-svn: 39763

llvm-svn: 39761

FI's created the write way to represent Mips stack

llvm-svn: 39760

llvm-svn: 39759

llvm-svn: 39758

llvm-svn: 39752

of size other than 4).

llvm-svn: 39743

llvm-svn: 39737

the sparc backend should be preferred when running on sparcs.

llvm-svn: 39142

llvm-svn: 38515

llvm-svn: 38514

llvm-svn: 38513

pedantic satisfaction level.

llvm-svn: 38512

llvm-svn: 38507

llvm-svn: 38501