llvm-svn: 40123

code that cross integer / floating point domains (e.g. generate pxor / pand for
logical ops on floating point value, movdqa to load / store floating point SSE
values). Given that, it's better to use movaps instead of movdqa and movups
instead of movdqu. They have the same latency but the "aps" variants are one
byte shorter.
If the domain crossing problem is a real performance issue, then we will have to
fix it with dynamic programming based isel.

llvm-svn: 40076

llvm-svn: 40071

Fix patterns so we isel the xorps, etc. for floating pt logical SSE ops. DAG combiner may fold away the (bit_convert (load)).

llvm-svn: 40070

InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033

llvm-svn: 40028

Use MOV instead of LEA to restore ESP if callee-saved frame size is 0; if previous instruction updates esp, fold it in.

llvm-svn: 40018

and stores that have a specified alignment of less than 16 bytes now use
instructions that support misaligned memory references.

llvm-svn: 40015

llvm-svn: 39998

llvm-svn: 39984

llvm-svn: 39978

llvm-svn: 39977

Missed the case where alloca is used but the stack size (not including callee-saved portion) is zero. Thanks Dan.

llvm-svn: 39974

llvm-svn: 39967

This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.

In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.

After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be 
thought as 'finished': I expect many small and not so small glitches
everywhere.

llvm-svn: 39855

llvm-svn: 39772

llvm-svn: 38514

pedantic satisfaction level.

llvm-svn: 38512

llvm-svn: 38507

in addition to the intrinsic forms. Add spill-folding entries for these new
instructions, and for the scalar min and max instrinsic instructions which
were missing. And add some preliminary ISelLowering code for using the new
non-intrinsic vector sqrt instruction, and fneg and fabs.

llvm-svn: 38478

zero if they see a target triple they don't understand.

llvm-svn: 38463

llvm-svn: 37960

llvm-svn: 37940

llvm-svn: 37923

Almost all occurrences of "bytecode" in the sources have been eliminated.

llvm-svn: 37913

their names are changed.

llvm-svn: 37876

llvm-svn: 37866

Still need to have JIT generate this code.

llvm-svn: 37863

llvm-svn: 37853

model to include f32 variants.  Some factoring
improvments forthcoming.

llvm-svn: 37847

the recent lowering changes, this allows types like <4 x double> to
be returned, using two vector registers.

llvm-svn: 37844

llvm-svn: 37801

llvm-svn: 37786

llvm-svn: 37784

llvm-svn: 37756

instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).

llvm-svn: 37728

extended vector types. Remove the special SDNode opcodes used for pre-legalize
vector operations, and the special MVT::Vector type used with them. Adjust
lowering and legalize to work with the normal SDNode kinds instead, and to
use the normal MVT functions to work with vector types instead of using the
two special operands that the pre-legalize nodes held.

This allows pre-legalize and post-legalize DAGs, and the code that operates
on them, to be more consistent. Pre-legalize vector operators can be handled
more consistently with scalar operators. And, -view-dag-combine1-dags and
-view-legalize-dags now look prettier for vector code.

llvm-svn: 37719

between SSE1 instructions and their respective SSE2 analogues.

llvm-svn: 37718

llvm-svn: 37717

llvm-svn: 37716