llvm-svn: 77238

implementations that need it, rearrange ELFTAI.

llvm-svn: 77236

llvm-svn: 77233

llvm-svn: 77232

llvm-svn: 77231

convertToThreeAddress can't handle Thumb2 instructions (which don't have same address mode as ARM instructions).

llvm-svn: 77230

llvm-svn: 77229

llvm-svn: 77227

llvm-svn: 77222

llvm-svn: 77221

This also fixes potential problems in ARMBaseInstrInfo routines not recognizing thumb1 instructions when 32-bit and 16-bit instructions mix.

llvm-svn: 77218

llvm-svn: 77217

Some libcall names are same, so they were getting printed twice.

llvm-svn: 77215

project.

llvm-svn: 77213

not in mergable

llvm-svn: 77210

llvm-svn: 77208

header even though there is only one COFF target.

llvm-svn: 77204

llvm-svn: 77203

llvm-svn: 77202

llvm-svn: 77201

llvm-svn: 77199

llvm-svn: 77198

llvm-svn: 77197

should know about them.  PECoff doesn't share these, and I want all sections
to be created by object-file-specific code.

llvm-svn: 77196

after their associated opcodes rather than before. This makes them
a little easier to read.

llvm-svn: 77194

llvm-svn: 77193

llvm-svn: 77191

llvm-svn: 77187

instead.

llvm-svn: 77186

instead and drive things based off of that.

llvm-svn: 77184

llvm-svn: 77182

llvm-svn: 77181

llvm-svn: 77179

fixed incorrect lowering of ISD::SUB node. SUB has only one result value.
It wasn't caught during tests because we never got a sub generated, (i8 was always getting promoted to int, which in turn was broken into subc/sube). Though the optimizer leaves an i8 sub now. 

llvm-svn: 77178

Use the right instructions to copy between GPR and the more strictive tGPR classes. t2MOV does not match the RC requirements.

llvm-svn: 77175

llvm-svn: 77174

llvm-svn: 77173

Rename tMOVhi2lor to tMOVgpr2tgpr. It's not moving from a high register to a low register. It's moving from a GPR register class to a more restrictive tGPR class. Also change tMOVlor2hir, and tMOVhir2hir.

llvm-svn: 77172

change.

llvm-svn: 77171

llvm-svn: 77169