coalescer) handle sub-register classes.
- Add heuristics to avoid non-profitable cse. Given the current lack of live
  range splitting, avoid cse when an expression has PHI use and the would be
  new use is in a BB where the expression wasn't already being used.

llvm-svn: 98043

Don't waste time trying to CSE labels, phis, inline asm. Definitely avoid cse implicit-def for obvious performance reason.

llvm-svn: 98009

llvm-svn: 98007

llvm-svn: 97861

llvm-svn: 97747

Look ahead a bit to determine if a physical register def that is not marked dead is really alive. This is necessary to catch a lot of common cse opportunities for targets like x86.

llvm-svn: 97706

Fix a logic error. An instruction that has a live physical register def cannot be CSE'ed, but it *can* be used to replace a common subexpression.

llvm-svn: 97688

Re-apply r97667 but with a little bit of thought put into the patch. This implements a special DenseMapInfo trait for DenseMap<MachineInstr*> that compare the value of the MachineInstr rather than the pointer value. Since the hashing and equality test functions ignore defs it's useful for doing CSE kind optimization.

llvm-svn: 97678

llvm-svn: 97673

llvm-svn: 97667

Machine CSE work in progress. It's doing some CSE now. But implicit def of physical registers are getting in the way.

llvm-svn: 97664

llvm-svn: 97635

llvm-svn: 97577

llvm-svn: 97543