llvm-svn: 95915

use a multipattern that generates both the 1-byte and 4-byte 
versions from the same defm

llvm-svn: 95901

Sorry!

llvm-svn: 95892

A8.6.297

llvm-svn: 95885

llvm-svn: 95884

as the "Permanently UNDEFINED" instruction.

llvm-svn: 95873

fixes the remaining x86-64 jit failures afaik.

llvm-svn: 95867

r12b, etc) also encodes to a R/M value of 4, which is just
as illegal as ESP/RSP for the non-sib version an address.

This fixes x86-64 jit miscompilations of a bunch of programs.

llvm-svn: 95866

Stub out some dummy fixups to make things work.

We can now emit fixups like this:
	subl	$20, %esp               ## encoding: [0x83,0xec,A]
                                        ##   fixup A - offset: 2, value: 20, kind: fixup_1byte_imm

Emitting $20 as a single-byte fixup to be later resolved
by the assembler is ridiculous of course (vs just emitting
the byte) but this is a failure of the matcher, which 
should be producing an imm of 20, not an MCExpr of 20.

llvm-svn: 95860

and rename it to EmitImmediate.

llvm-svn: 95859

llvm-svn: 95858

llvm-svn: 95857

lowering and requires that certain types exist in ValueTypes.h.  Modified widening to
check if an op can trap and if so, the widening algorithm will apply only the op on
the defined elements.  It is safer to do this in widening because the optimizer can't
guarantee removing unused ops in some cases.

llvm-svn: 95823

code with lots of bitfields.

llvm-svn: 95809

x86_32-encoding.s in on expectation of it passing.

llvm-svn: 95806

llvm-svn: 95784

llvm-svn: 95781

displacement values.

llvm-svn: 95773

throughout the X86 encoder.

llvm-svn: 95771

even for the immediate case.  No functionality change.

llvm-svn: 95770

MCInst it came from.

llvm-svn: 95767

OutStreamer.AddBlankLine instead of textually.

llvm-svn: 95734

prefix which is part of the opcode encoding.

llvm-svn: 95729

Enhance the x86 backend to show the hex values of immediates in
comments when they are large.  For example:

        movl    $1072693248, 4(%esp)    ## imm = 0x3FF00000

llvm-svn: 95728

TableGen fragment refactoring.

Move some utility TableGen defs, classes, etc. into a common file so
they may be used my multiple pattern files.  We will use this for
the AVX specification to help with the transition from the current
SSE specification.

llvm-svn: 95727

A8.6.279

llvm-svn: 95713

llvm-svn: 95709

llvm-svn: 95708

A8.6.335 & A8.6.336

llvm-svn: 95703

llvm-svn: 95699

in X86-32 mode.  This is still required in x86-64 mode to avoid
forming [disp+rip] encoding.  Rewrite the SIB byte decision logic
to be actually understandable.

llvm-svn: 95693

a confusing idiom to check for ESP or RSP.

llvm-svn: 95690

llvm-svn: 95689

into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687

tMOVCCi pattern only valid for low registers, as the Thumb1 mov immediate to
register instruction only works with low registers. Allowing high registers
for the instruction resulted in the assembler choosing the wide (32-bit)
encoding for the mov, but LLVM though the instruction was only 16 bits wide,
so offset calculations for constant pools became incorrect, leading to
out of range constant pool entries.

llvm-svn: 95686

For disassembly only.

A8.6.300

llvm-svn: 95669

llvm-svn: 95650

llvm-svn: 95649

llvm-svn: 95634

llvm-svn: 95627