Implement a feature (-vector-unaligned-mem) to allow targets to
ignore alignment requirements for SIMD memory operands.  This
is useful on architectures like the AMD 10h that do not trap on
unaligned references if a status bit is twiddled at startup time.

llvm-svn: 93151

R11, and then asserting that the target was in R9.  Since R9 isn't reserved for
the target anymore, and is used as an argument, this patch changes the
assertion.

llvm-svn: 93065

Fix a critical bug in 64-bit atomic operation lowering for 32-bit. The results of the cmpxchg8b instructions are being thrown away when it branches back to the top of the checking loop. This means the loop always compares against the old value and this can result in a dead lock.

llvm-svn: 93028

llvm-svn: 93020

putting relocations into the constant pool - this isn't needed
for correctness and in the rare occasion it happens would pull
us out of fast isel for the block.

If fast-isel application startup time ever becomes an issue we
can add better support for these addresses instead of bailing.

llvm-svn: 92995

1. CMPXCHG8B and CMPXCHG16B did not specify implicit physical register defs and uses.
2. LCMPXCHG8B is loading 64 bit memory, not 32 bit.

llvm-svn: 92985

llvm-svn: 92972

add it to the constant pool for fast-isel. We already
don't add it for the normal case.

llvm-svn: 92934

Fix a minor regression from my dag combiner changes. One more place which needs to look pass truncates.

llvm-svn: 92885

(OP (trunc x), (trunc y)) -> (trunc (OP x, y))

Unfortunately this simple change causes dag combine to infinite looping. The problem is the shrink demanded ops optimization tend to canonicalize expressions in the opposite manner. That is badness. This patch disable those optimizations in dag combine but instead it is done as a late pass in sdisel.

This also exposes some deficiencies in dag combine and x86 setcc / brcond lowering. Teach them to look pass ISD::TRUNCATE in various places.

llvm-svn: 92849

llvm-svn: 92771

llvm-svn: 92760

llvm-svn: 92694

llvm-svn: 92654

llvm-svn: 92653

llvm-svn: 92651

llvm-svn: 92648

llvm-svn: 92647

llvm-svn: 92644

clear what information these functions are actually using.

This is also a micro-optimization, as passing a SDNode * around is
simpler than passing a { SDNode *, int } by value or reference.

llvm-svn: 92564

operators. Eli pointed out that it's not obvious what that
would mean.

llvm-svn: 92555

(or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)

The isel patterns may not catch all the cases if general dag combine has reduced width of source operands.

llvm-svn: 92513

llvm-svn: 92511

lets the test-elimination work in more conditional-move cases.

llvm-svn: 92508

rules as normal add, and, or, etc.

llvm-svn: 92507

This lets isel fold loads into them in more cases.

llvm-svn: 92506

llvm-svn: 92265

llvm-svn: 92184

do illegal stuff around it.  No testcase because the issue is very fragile.

llvm-svn: 92167

llvm-svn: 91976

interesting part of this is the divrem changes, which are
already tested by CodeGen/X86/divrem.ll.

llvm-svn: 91975

static inline functions with macros.

llvm-svn: 91973

instead use the appropriate subreggy thing.  This generates identical
code on some large apps (thanks to Evan's cross class coalescing
stuff he did back in july).  This means that MOV16r0 can go away
completely in the future soon.

llvm-svn: 91972

because the Visual C++ build does not build .c files as C99

llvm-svn: 91935

Made LEA memory operands emit only 4 MCInst operands.
Made the scale operand equal 1 for instructions that have no
SIB byte.

llvm-svn: 91919

Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size.

llvm-svn: 91910

llvm-svn: 91908

return partial registers. This affected the back-end lowering code some.

Also patch up some places I missed before in the "get" functions.

llvm-svn: 91880

with symbols in AuroraUX's global namespace.

llvm-svn: 91879

llvm-svn: 91878