- Oct 30, 2011
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Craig Topper authored
llvm-svn: 143319
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Benjamin Kramer authored
X86: Emit logical shift by constant splat of <16 x i8> as a <8 x i16> shift and zero out the bits where zeros should've been shifted in. llvm-svn: 143315
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Nadav Rotem authored
Fix pr11266. On x86: (shl V, 1) -> add V,V Hardware support for vector-shift is sparse and in many cases we scalarize the result. Additionally, on sandybridge padd is faster than shl. llvm-svn: 143311
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- Oct 29, 2011
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Dan Gohman authored
llvm-svn: 143262
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- Oct 28, 2011
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Dan Gohman authored
fixes: Use a separate register, instead of SP, as the calling-convention resource, to avoid spurious conflicts with actual uses of SP. Also, fix unscheduling of calling sequences, which can be triggered by pseudo-two-address dependencies. llvm-svn: 143206
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Duncan Sands authored
it fixes the dragonegg self-host (it looks like gcc is miscompiled). Original commit messages: Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW on every node as it legalizes them. This makes it easier to use hasOneUse() heuristics, since unneeded nodes can be removed from the DAG earlier. Make LegalizeOps visit the DAG in an operands-last order. It previously used operands-first, because LegalizeTypes has to go operands-first, and LegalizeTypes used to be part of LegalizeOps, but they're now split. The operands-last order is more natural for several legalization tasks. For example, it allows lowering code for nodes with floating-point or vector constants to see those constants directly instead of seeing the lowered form (often constant-pool loads). This makes some things somewhat more complicated today, though it ought to allow things to be simpler in the future. It also fixes some bugs exposed by Legalizing using RAUW aggressively. Remove the part of LegalizeOps that attempted to patch up invalid chain operands on libcalls generated by LegalizeTypes, since it doesn't work with the new LegalizeOps traversal order. Instead, define what LegalizeTypes is doing to be correct, and transfer the responsibility of keeping calls from having overlapping calling sequences into the scheduler. Teach the scheduler to model callseq_begin/end pairs as having a physical register definition/use to prevent calls from having overlapping calling sequences. This is also somewhat complicated, though there are ways it might be simplified in the future. This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others. Please direct high-level questions about this patch to management. Delete #if 0 code accidentally left in. llvm-svn: 143188
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Dan Gohman authored
on every node as it legalizes them. This makes it easier to use hasOneUse() heuristics, since unneeded nodes can be removed from the DAG earlier. Make LegalizeOps visit the DAG in an operands-last order. It previously used operands-first, because LegalizeTypes has to go operands-first, and LegalizeTypes used to be part of LegalizeOps, but they're now split. The operands-last order is more natural for several legalization tasks. For example, it allows lowering code for nodes with floating-point or vector constants to see those constants directly instead of seeing the lowered form (often constant-pool loads). This makes some things somewhat more complicated today, though it ought to allow things to be simpler in the future. It also fixes some bugs exposed by Legalizing using RAUW aggressively. Remove the part of LegalizeOps that attempted to patch up invalid chain operands on libcalls generated by LegalizeTypes, since it doesn't work with the new LegalizeOps traversal order. Instead, define what LegalizeTypes is doing to be correct, and transfer the responsibility of keeping calls from having overlapping calling sequences into the scheduler. Teach the scheduler to model callseq_begin/end pairs as having a physical register definition/use to prevent calls from having overlapping calling sequences. This is also somewhat complicated, though there are ways it might be simplified in the future. This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others. Please direct high-level questions about this patch to management. llvm-svn: 143177
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- Oct 27, 2011
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Kevin Enderby authored
not depend on In32BitMode. Use the sysexitq mnemonic for the version with the REX.W prefix and only allow it only In64BitMode. rdar://9738584 llvm-svn: 143112
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Lang Hames authored
llvm-svn: 143080
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- Oct 26, 2011
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Rafael Espindola authored
Patch by Sanjoy Das. llvm-svn: 143064
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Rafael Espindola authored
MORESTACK_RET_RESTORE_R10; which are lowered to a RET and a RET followed by a MOV respectively. Having a fake instruction prevents the verifier from seeing a MachineBasicBlock end with a non-terminator (MOV). It also prevents the rather eccentric case of a MachineBasicBlock ending with RET but having successors nevertheless. Patch by Sanjoy Das. llvm-svn: 143062
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- Oct 24, 2011
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Eli Friedman authored
llvm-svn: 142841
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Craig Topper authored
llvm-svn: 142779
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- Oct 23, 2011
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Craig Topper authored
llvm-svn: 142741
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Craig Topper authored
llvm-svn: 142738
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Craig Topper authored
llvm-svn: 142737
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- Oct 22, 2011
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Nadav Rotem authored
SHL inserts zeros from the right, thus even when the original sign_extend_inreg value was of 1-bit, we need to sra. llvm-svn: 142724
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- Oct 21, 2011
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Craig Topper authored
Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with custom isel lowering code. llvm-svn: 142642
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- Oct 20, 2011
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- Oct 19, 2011
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Craig Topper authored
llvm-svn: 142480
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Eric Christopher authored
This reverts commit 494f7ac3e8d2ab3d94e52317abf9c42a949fe1f3. llvm-svn: 142455
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Eric Christopher authored
I'll remove/rename the option in a few days. llvm-svn: 142439
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Lang Hames authored
Teach fast isel about vector stores, and make DoSelectCall return false when it fails to emit a store. This fixes <rdar://problem/10215997>. llvm-svn: 142432
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- Oct 18, 2011
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Duncan Sands authored
build with gcc-4.6. llvm-svn: 142350
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David Meyer authored
llvm-svn: 142338
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- Oct 17, 2011
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Craig Topper authored
Don't use inline assembly in 64-bit Visual Studio. Unfortunately, this means that cpuid leaf 7 can't be queried on versions of Visual Studio earlier than VS 2008 SP1. Fixes PR11147. llvm-svn: 142177
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- Oct 16, 2011
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Craig Topper authored
llvm-svn: 142141
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Benjamin Kramer authored
<stdin>:1:12: error: register %rax is only available in 64-bit mode incl %rax ^~~~ llvm-svn: 142137
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Benjamin Kramer authored
X86AsmParser: Synthesize EndLoc for tokens out of StartLoc + Length and print ranges for invalid operands. <stdin>:1:4: error: invalid instruction mnemonic 'abc' abc incl %edi ^~~ llvm-svn: 142135
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Craig Topper authored
llvm-svn: 142122
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Craig Topper authored
Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr. llvm-svn: 142117
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Chris Lattner authored
the X86 asmparser to produce ranges in the one case that was annoying me, for example: test.s:10:15: error: invalid operand for instruction movl 0(%rax), 0(%edx) ^~~~~~~ It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use ranges where appropriate if someone is interested. llvm-svn: 142106
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Craig Topper authored
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen llvm-svn: 142105
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Craig Topper authored
Add X86 feature detection support for BMI instructions. Added new cpuid function for accessing leafs with sub leafs specified in ECX. Also added code to keep track of the max cpuid level supported in both basic and extended leaves and qualified the existing cpuid calls and the new call to leaf 7. llvm-svn: 142089
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- Oct 15, 2011
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Craig Topper authored
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension. llvm-svn: 142082
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Benjamin Kramer authored
llvm-svn: 142073
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- Oct 14, 2011
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Evan Cheng authored
llvm-svn: 141988
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Craig Topper authored
llvm-svn: 141947
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Craig Topper authored
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell. llvm-svn: 141939
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Jakob Stoklund Olesen authored
TableGen infers unmodeled side effects on instructions without a pattern. Fix some instruction definitions where that was overlooked. Also raise an error if a rematerializable instruction has unmodeled side effects. That doen't make any sense. llvm-svn: 141929
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