The function needs to scan the implicit operands anyway, so no
performance is won by caching the number of implicit operands added to
an instruction.

This also fixes a bug when adding operands after an implicit operand has
been added manually.  The NumImplicitOps count wasn't kept up to date.

MachineInstr::addOperand() will now consistently place all explicit
operands before all the implicit operands, regardless of the order they
are added.  It is possible to change an MI opcode and add additional
explicit operands.  They will be inserted before any existing implicit
operands.

The only exception is inline asm instructions where operands are never
reordered.  This is because of a hack that marks explicit clobber regs
on inline asm as <implicit-def> to please the fast register allocator.
This hack can go away when InstrEmitter and FastIsel can add exact
<dead> flags to physreg defs.

llvm-svn: 140744

Upon further review, most of the EH code should remain written at the IR
level. The part which breaks SSA form is the dispatch table, so that part will
be moved to the back-end.

llvm-svn: 140730

when there is both a catch and a cleanup.  Correct the comment.

llvm-svn: 140686

llvm-svn: 140678

llvm-svn: 140677

This intrinsic is used to pass the index of the function context to the back-end
for further processing. The back-end is in charge of filling in the rest of the
entries.

llvm-svn: 140676

The DWARF exception pass uses the call site information, which is set up here. A
pre-RA pass is too late for it to use this information. So create and setup the
function context here, and then insert the call site values here (and map the
call sites for the DWARF EH pass). This is simpler than the original pass, and
doesn't make the CFG lose its SSA-ness.

It's a win-win-win-win-lose-win-win situation.

llvm-svn: 140675

We may need an SjLj EH preparation pass for some call site information, at least
in the short term.

llvm-svn: 140674

No functional change intended.

llvm-svn: 140664

I'll clean up the source in the next commit.

llvm-svn: 140663

current IR-level pass.

The old SjLj EH pass has some problems, especially with the new EH model. Most
significantly, it violates some of the new restrictions the new model has. For
instance, the 'dispatch' table wants to jump to the landing pad, but we cannot
allow that because only an invoke's unwind edge can jump to a landing pad. This
requires us to mangle the code something awful. In addition, we need to keep the
now dead landingpad instructions around instead of CSE'ing them because the
DWARF emitter uses that information (they are dead because no control flow edge
will execute them - the control flow edge from an invoke's unwind is superceded
by the edge coming from the dispatch).

Basically, this pass belongs not at the IR level where SSA is king, but at the
code-gen level, where we have more flexibility.

llvm-svn: 140646

a suboptimal schedule.

llvm-svn: 140643

Naming conventions consistency. No functional change.

llvm-svn: 140636

Add a new method: getAnyExtOrTrunc and use it to replace the manual check.

llvm-svn: 140603

while the decision is to bit-pack small values.

llvm-svn: 140601

Fix emission of debug data for global variables. getContext() on DIGlobalVariables is not valid any more.

llvm-svn: 140539

Many targets use pseudo instructions to help register allocation.  Like
the COPY instruction, these pseudos can be expanded after register
allocation.  The early expansion can make life easier for PEI and the
post-ra scheduler.

This patch adds a hook that is called for all remaining pseudo
instructions from the ExpandPostRAPseudos pass.

llvm-svn: 140472

SDNodes may return values which are wider than the incoming element types. In
this patch we fix the integer promotion of these nodes.

Fixes spill-q.ll when running -promote-elements.

llvm-svn: 140471

No functional change intended.

llvm-svn: 140470

I'll fix the file contents in the next commit.

This pass is currently expanding the COPY and SUBREG_TO_REG pseudos. I
am going to add a hook so targets can expand more pseudo-instructions
after register allocation.

Many targets have pseudo-instructions that assist the register
allocator.  They can be expanded after register allocation, before PEI
and PostRA scheduling.

llvm-svn: 140469

Implement Duncan's suggestion to use the result of getSetCCResultType if it is legal
(this is always the case for scalars), otherwise use the promoted result type.

Fix test/CodeGen/X86/vsplit-and.ll when promote-elements is enabled.

llvm-svn: 140464

When generating the trunc-store of i1's, we need to use the vector type and not
the scalar type.

This patch fixes the assertion in CodeGen/Generic/bool-vector.ll when
running with -promote-elements.

llvm-svn: 140463

This exposes a -segmented-stacks bug.

llvm-svn: 140429

PR10998: It is not legal to sink an instruction past the terminator of a block; make sure we don't do that.

llvm-svn: 140428

DecomposeMERGE_VALUES to "know" that results are legalized in
a particular order, by passing it the number of the result
being legalized (the type legalization core provides this, it
just needs to be passed on).

llvm-svn: 140373

integer-promotion of CONCAT_VECTORS.

Test: test/CodeGen/X86/widen_shuffle-1.ll

This patch fixes the above tests (when running in with -promote-elements).

llvm-svn: 140372

worklist, as it may be possible to perform further optimization on them.

llvm-svn: 140349

Sometimes register class constraints are trivial, like GR32->GR32_NOSP,
or GPR->rGPR.  Teach InstrEmitter to simply constrain the virtual
register instead of emitting a copy in these cases.

Normally, these copies are handled by the coalescer.  This saves some
coalescer work.

llvm-svn: 140340

The function will refuse to use a register class with fewer registers
than MinNumRegs.  This can be used by clients to avoid accidentally
increase register pressure too much.

The default value of MinNumRegs=0 doesn't affect how constrainRegClass()
works.

llvm-svn: 140339

llvm-svn: 140318

Few weeks ago, llvm completely inverted the debug info graph. Earlier each debug info node used to keep track of its compile unit, now compile unit keeps track of important nodes. One impact of this change is that the global variable's do not have any context, which should be checked before deciding to use AT_specification DIE.

llvm-svn: 140282

This inserts a cleanup landingpad instruction and a resume to mimic the old
unwind instruction.

llvm-svn: 140277

llvm-svn: 140275

Vector SetCC result types need to be type-legalized.
This code worked before because scalar result types are known to be legal.

llvm-svn: 140249

This is still a hack until we can teach tblgen to generate the
optional CPSR operand rather than an implicit CPSR def. But the
strangeness is now limited to the selection DAG. ADD/SUB MI's no
longer have implicit CPSR defs, nor do we allow flag setting variants
of these opcodes in machine code. There are several corner cases to
consider, and getting one wrong would previously lead to nasty
miscompilation. It's not the first time I've debugged one, so this
time I added enough verification to ensure it won't happen again.

llvm-svn: 140228

subvector inserts and extracts. Initial patch by Rackover, Zvi with
some tweak done by me.

llvm-svn: 140204

No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.

llvm-svn: 140160

Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile

llvm-svn: 140134

llvm-svn: 140133

llvm-svn: 139994