llvm-svn: 119482

llvm-svn: 119463

llvm-svn: 119462

should get the submode from the load/store multiple instruction's opcode.

llvm-svn: 119461

instructions have to distinguish between lists of single- and double-precision
registers in order for the ASM matcher to do a proper job. In all other
respects, a list of single- or double-precision registers are the same as a list
of GPR registers.

llvm-svn: 119460

class, uses DominatorTree which is an analysis.  This change moves all of
the tricky hasConstantValue logic to SimplifyInstruction, and replaces it
with a very simple literal implementation.  I already taught users of
hasConstantValue that need tricky stuff to use SimplifyInstruction instead.
I didn't update InlineFunction because the IR looks like it might be in a
funky state at the point it calls hasConstantValue, which makes calling
SimplifyInstruction dangerous since it can in theory do a lot of tricky
reasoning.  This may be a pessimization, for example in the case where
all phi node operands are either undef or a fixed constant.

llvm-svn: 119459

While there, add a note about an inefficiency I noticed.

llvm-svn: 119458

rather than hasConstantValue.

llvm-svn: 119457

systematically, CollapsePhi will always return null here.  Note
that CollapsePhi did an extra check, isSafeReplacement, which
the SimplifyInstruction logic does not do.  I think that check
was bogus - I guess we will soon find out!  (It was originally
added in commit 41998 without a testcase).

llvm-svn: 119456

This fixes some extreme compile times on unrolled sha512 code.

llvm-svn: 119455

operands in a variadic instruction.

llvm-svn: 119446

"getRegisterListOpValue" logic. If the registers are double or single precision,
the value returned is suitable for VLDM/VSTM.

llvm-svn: 119435

llvm-svn: 119433

llvm-svn: 119403

a different pass, the complicated interaction between cmov expansion
and fast isel is no longer a concern.

llvm-svn: 119400

Patch by Louis Zhuang!

llvm-svn: 119394

llvm-svn: 119386

llvm-svn: 119385

Next: Add support for the !HasDotLocAndDotFile case to the MCAsmStreamer
and then switch codegen to use it.

llvm-svn: 119384

easier to debug, and to avoid complications when the CFG changes
in the middle of the instruction selection process.

llvm-svn: 119382

Always spill the full representative register at any point where any subregister
is live.

This fixes PR8620 which caused the old logic to get confused and not spill
anything at all.

The fundamental problem here is that the coalescer is too aggressive about
physical register coalescing. It sometimes makes it impossible to allocate
registers without these emergency spills.

llvm-svn: 119375

llvm-svn: 119374

llvm-svn: 119362

The system API's will be shifted over to returning an error_code, and returning
other return values as out parameters to the function.

Code that needs to check error conditions will use the errc enum values which
are the same as the posix_errno defines (EBADF, E2BIG, etc...), and are
compatable with the error codes in WinError.h due to some magic in system_error.

An example would be:

if (error_code ec = KillEvil("Java")) { // error_code can be converted to bool.
  handle_error(ec);
}

llvm-svn: 119360

llvm-svn: 119354

rather than calling hasConstantValue.  No intended functionality change.

llvm-svn: 119352

over a phi node by applying it to each operand may be wrong if the
operation and the phi node are mutually interdependent (the testcase
has a simple example of this).  So only do this transform if it would
be correct to perform the operation in each predecessor of the block
containing the phi, i.e. if the other operands all dominate the phi.
This should fix the FFMPEG snow.c regression reported by İsmail Dönmez.

llvm-svn: 119347

llvm-svn: 119328

llvm-svn: 119325

- Add encodings to the *LDMIA_RET instrs. Probably not needed...

llvm-svn: 119323

llvm-svn: 119321

(and likely) wrong about anyhow.

llvm-svn: 119320

branches to be emitted as:

 	bne cr0, 2
instead of:
 	bne cr0, $+8

llvm-svn: 119317

'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>

llvm-svn: 119310

llvm-svn: 119309

llvm-svn: 119308

these instructions to be encoded with getMachineOpValue.
This unbreaks ExecutionEngine/2003-01-04-ArgumentBug.ll 
when running on a G5

llvm-svn: 119307

Use amazing new function call technology instead of writing identical code in
multiple places.

This fixes PR8604.

llvm-svn: 119306

The live range of a register defined by an early clobber starts at the use slot,
not the def slot.

Except when it is an early clobber tied to a use operand. Then it starts at the
def slot like a standard def.

llvm-svn: 119305

llvm-svn: 119295