When splitting global live ranges, it is now possible to split for
multiple destination intervals at once. Previously, we only had the main
and stack intervals.

Each edge bundle is assigned to a split candidate, and splitAroundRegion
will insert copies between the candidate intervals and the stack
interval as needed.

The multi-way splitting is used to split around compact regions when
enabled with -compact-regions. The best candidate register still gets
all the bundles it wants, but everything outside the main interval is
first split around compact regions before we create single-block
intervals.

Compact region splitting still causes some regressions, so it is not
enabled by default.

llvm-svn: 136186

llvm-svn: 136178

These copies would coalesce easily, but the resulting value would be
defined by a deleted instruction. Now we also remove the undefined value
number from the destination register.

This fixes PR10503.

llvm-svn: 136174

On x86 we can't encode an immediate LHS of a sub directly. If the RHS comes from a XOR with a constant we can
fold the negation into the xor and add one to the immediate of the sub. Then we can turn the sub into an add,
which can be commuted and encoded efficiently.

This code is generated for __builtin_clz and friends.

llvm-svn: 136167

different from the previous 128-bit because they work in lanes.
Update a few comments and add testcases

llvm-svn: 136157

llvm-svn: 136156

Allow the rot_imm operand to be optional. This sets the stage for refactoring
away the "rr" versions from the multiclasses and replacing them with Pat<>s.

llvm-svn: 136154

Start of cleaning this up a bit. First step is to remove the encoder hook by
storing the operand as the bits it'll actually encode to so it can just be
directly used. Map it to the assembly source values 8/16/24 when we print it.

llvm-svn: 136152

Prevent x86-specific DAGCombine from creating nodes with illegal type (which could not be selected).  Fixes a minor isel issue that was breaking the testcase from r136130.

llvm-svn: 136148

llvm-svn: 136145

Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE.

llvm-svn: 136141

llvm-svn: 136138

llvm-svn: 136132

llvm-svn: 136130

obviously big endian. :-)
PR10502

llvm-svn: 136111

llvm-svn: 136110

llvm-svn: 136109

llvm-svn: 136108

While extracting lexical scopes from machine instruction stream, work on one machine basic block at a time. 

llvm-svn: 136106

rdar://9842203

llvm-svn: 136102

exit. Added an interfaces for querying either the loop's exact/max
backedge taken count or a specific loop exit's not-taken count.

llvm-svn: 136100

llvm-svn: 136098

llvm-svn: 136096

No intendeded functional change. Just cleaning up a bit to make things more
self-consistent in layout and style.

llvm-svn: 136095

llvm-svn: 136091

llvm-svn: 136090

a GNU userspace).

llvm-svn: 136085

llvm-svn: 136083

llvm-svn: 136082

llvm-svn: 136080

way for i1 and vector of i1 types.  Use these to make some code
more self-documenting.

llvm-svn: 136079

llvm-svn: 136065

llvm-svn: 136051

support for 256-bit versions (but no instruction selection yet, coming next).

llvm-svn: 136050

llvm-svn: 136049

llvm-svn: 136048

27 insertions(+), 62 deletions(-)

llvm-svn: 136047

When dead code elimination deletes a PHI value, the virtual register may
split into multiple connected components. In that case, revert each
component to the RS_Assign stage.

The new components are guaranteed to be smaller (the original value
numbers are distributed among the components), so this will always be
making progress. The components are now allowed to evict other live
ranges or be split again.

llvm-svn: 136034

llvm-svn: 136031

llvm-svn: 136030