Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit.

llvm-svn: 157898

llvm-svn: 157896

Use sse_load_f32/64 for scalar FMA3 intrinsic patterns instead of 128-bit loads to match instruction behavior.

llvm-svn: 157895

llvm-svn: 157894

llvm-svn: 157885

llvm-svn: 157872

llvm-svn: 157867

llvm-svn: 157866

llvm-svn: 157865

custom-lower unaligned load and store nodes.

llvm-svn: 157864

llvm-svn: 157863

This is the first of a series of patches which make changes to the backend to
emit unaligned load/store instructions (lwl,lwr,swl,swr) during instruction
selection.

llvm-svn: 157862

the MachineOperand type has a valid offset. 

llvm-svn: 157861

No functional change intended.

Sorry for the churn. The iterator classes are supposed to help avoid
giant commits like this one in the future. The TableGen-produced
register lists are getting quite large, and it may be necessary to
change the table representation.

This makes it possible to do so without changing all clients (again).

llvm-svn: 157854

then DestReg is undefined.

llvm-svn: 157840

MCRegAliasIterator can optionally visit the register itself, allowing
for simpler code.

llvm-svn: 157837

This patch will optimize the following:
  sub r1, r3
  cmp r3, r1 or cmp r1, r3
  bge L1
TO
  sub r1, r3
  bge L1 or ble L1

If the branch instruction can use flag from "sub", then we can eliminate
the "cmp" instruction.

llvm-svn: 157831

Factor out the expansion code into a function.
This change is to be enabled in clang.

rdar://9877866

llvm-svn: 157830

This implements codegen support for accesses to thread-local variables
using the local-dynamic model, and adds a clean-up pass so that the base
address for the TLS block can be re-used between local-dynamic access on
an execution path.

llvm-svn: 157818

llvm-svn: 157805

Remove fadd(fmul) patterns for FMA3. This needs to be implemented by paying attention to FP_CONTRACT and matching @llvm.fma which is not available yet. This will allow us to enablle intrinsic use at least though.

llvm-svn: 157804

llvm-svn: 157802

llvm-svn: 157801

llvm-svn: 157799

We handle struct byval by inserting a pseudo op, which will be expanded to a
loop at ExpandISelPseudos.
A separate patch for clang will be submitted to enable struct byval.

rdar://9877866

llvm-svn: 157793

llvm-svn: 157783

Patch by Yiannis Tsiouris!

llvm-svn: 157757

This patch will optimize the following
        movq    %rdi, %rax
        subq    %rsi, %rax
        cmovsq  %rsi, %rdi
        movq    %rdi, %rax
to
        cmpq    %rsi, %rdi
        cmovsq  %rsi, %rdi
        movq    %rdi, %rax

Perform this optimization if the actual result of SUB is not used.

rdar: 11540023
llvm-svn: 157755

Reg-units are named after their root registers, and most units have a
single root, so they simply print as 'AL', 'XMM0', etc. The rare dual
root reg-units print as FPSCR~FPSCR_NZCV, FP0~ST7, ...

The printing piggybacks on the existing register name tables, so no
extra const data space is required.

llvm-svn: 157754

llvm-svn: 157752

It was renamed in gcc/gas a while ago and causes all kinds of
confusion because it was named differently in llvm and clang.

llvm-svn: 157745

I disabled FMA3 autodetection, since the result may differ from expected for some benchmarks.
I added tests for GodeGen and intrinsics.
I did not change llvm.fma.f32/64 - it may be done later.

llvm-svn: 157737

llvm-svn: 157731

CPU16RegsRegClass and CPURARegRegClass available. Add definition of mips16
jalr instruction.

Patch by Reed Kotler.

llvm-svn: 157730

This code is covered by test/CodeGen/ARM/arm-modifier.ll.

llvm-svn: 157720

Switch to MCSuperRegIterator while we're there.

llvm-svn: 157717

Patch by Jack Carter.

llvm-svn: 157709

It is better to address sub-registers directly by name instead of
relying on their position in the sub-register list.

llvm-svn: 157703

it's pointed out that R11 can be used for magic things, and doing things just for 64-bit registers is silly.  Just optimize 3 more.

llvm-svn: 157699

integer registers.  This is already supported by the fastcc convention, but it doesn't
hurt to support it in the standard conventions as well.

In cases where we can cheat at the calling convention, this allows us to avoid returning
things through memory in more cases.

llvm-svn: 157698