- This fixed a number of bugs in if-converter, tail merging, and post-allocation
  scheduler. If-converter now runs branch folding / tail merging first to
  maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
  register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
  change the instruction ordering in the IT block (since IT mask has been
  finalized). It also ensures no other instructions can be scheduled between
  instructions in the IT block.

This is not yet enabled.

llvm-svn: 106344

llvm-svn: 106342

llvm-svn: 106336

llvm-svn: 106327

(as suggested in radar 8104405).

llvm-svn: 106318

llvm-svn: 106314

limit on the offset that can be materialized without using the register
scavenger.

llvm-svn: 106312

llvm-svn: 106311

original basic block. This avoids trouble with examining
instructions in other basic blocks which haven't been
assigned registers yet.

llvm-svn: 106310

ARM tail calls.  Don't know if it works, but it
doesn't break Darwin.

llvm-svn: 106309

basic tests.

This has been well tested on Darwin but not elsewhere.
It should work provided the linker correctly resolves
  B.W  <label in other function>
which it has not seen before, at least from llvm-based
compilers.  I'm leaving the arm-tail-calls switch in
until I see if there's any problems because of that;
it might need to be disabled for some environments.

llvm-svn: 106299

MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.

llvm-svn: 106296

Not turning them on yet.

llvm-svn: 106295

does for {flags}. If we create virtual registers of the CCR class, RegAllocFast
may try to spill them, and we can't do that.

llvm-svn: 106289

SDNode *, since it doesn't care about the ResNo value.

llvm-svn: 106282

llvm-svn: 106280

llvm-svn: 106279

llvm-svn: 106278

llvm-svn: 106273

to track a node over CSE events. This fixes PR7368.

llvm-svn: 106266

llvm-svn: 106264

which is faster, simpler, and less surprising.

llvm-svn: 106263

be done incrementally and intermixed with the adding of more
AVX instructions. This is a first step in that direction

llvm-svn: 106251

addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.

This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.

llvm-svn: 106243

ISD::MEMBARRIER. v7 and v7 ARM mode continue to use the custom lowering.

llvm-svn: 106204

previously would result in 'cannot yet select' errors.

llvm-svn: 106199

TLVP:

movl _a@TLVP, %eax

Daniel: Please review if you get a chance.
llvm-svn: 106194

llvm-svn: 106173

This is before LiveVariables anyway, where these kill flags are recalculated.

llvm-svn: 106157

now, so there's no need to disable them.

llvm-svn: 106155

llvm-svn: 106102

Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler.

llvm-svn: 106091

will conflict with another live range. The place which creates this scenerio is
the code in X86 that lowers a select instruction by splitting the MBBs. This
eliminates the need to check from the bottom up in an MBB for live pregs.

llvm-svn: 106066

a relative address.

llvm-svn: 106064

llvm-svn: 106058

call must not be callee-saved; following x86, add a new
regclass to represent this.  Also fixes a couple of bugs.
Still disabled by default; Thumb doesn't work yet.

llvm-svn: 106053

flag argument to addReg is not the same format as flags attached
to MachineOperand, although both have the same info.  I don't
think this actually mattered; the bootstrap failure did not
reproduce on the next run anyway.

llvm-svn: 106049

Nelson Elhage!

llvm-svn: 106031

llvm-svn: 106030

llvm-svn: 105994