llvm-svn: 121853

llvm-svn: 121850

llvm-svn: 121849

llvm-svn: 121820

immediate versions.

llvm-svn: 121819

llvm-svn: 121815

llvm-svn: 121812

llvm-svn: 121809

particular, we want

   ldr r2, [r3]

to be equivalent to

   ldr r2, [r3, #0]

and not

   ldr r2, [r3, r0]

llvm-svn: 121808

llvm-svn: 121798

llvm-svn: 121797

is the addition of the FoldableAsLoad & Rematerializable flags to some of the
load instructions. ARM has these flags set for them.

llvm-svn: 121794

llvm-svn: 121792

llvm-svn: 121790

llvm-svn: 121789

llvm-svn: 121788

llvm-svn: 121784

llvm-svn: 121780

llvm-svn: 121772

llvm-svn: 121769

llvm-svn: 121765

instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.

The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.

There are some obvious cleanups here, which will happen shortly.

llvm-svn: 121747

llvm-svn: 121746

Second attempt at make Thumb2 LEAs pseudos.  This time, perform the lowering much later, which makes the entire
process cleaner.

llvm-svn: 121735

Use the same COPY_TO_REGCLASS approach as for the 2-register *_sfp instructions.
This change made a big difference in the code generated for the
CodeGen/Thumb2/cross-rc-coalescing-2.ll test: The coalescer is still doing
a fine job, but some instructions that were previously moved outside the loop
are not moved now.  It's using fewer VFP registers now, which is generally
a good thing, so I think the estimates for register pressure changed and that
affected the LICM behavior.  Since that isn't obviously wrong, I've just
changed the test file.  This completes the work for Radar 8711675.

llvm-svn: 121730

llvm-svn: 121729

llvm-svn: 121726

Make Thumb2 LEA-like instruction into pseudos, which map down to ADR.  Provide correct fixups for Thumb2 ADR,
which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup.

llvm-svn: 121721

llvm-svn: 121719

Jakob Olesen suggested that we can avoid the need for separate pseudo
instructions here by using COPY_TO_REGCLASS in the patterns.  The pattern
gets pretty ugly but it seems to work well.  Partial fix for Radar 8711675.

llvm-svn: 121718

Partial fix for Radar 8711675.

llvm-svn: 121716

llvm-svn: 121715

llvm-svn: 121714

In Thumb2, direct branches can be encoded as either a "short" conditional branch with a null predicate, or
as a "long" direct branch.  While the mnemonics are the same, they encode the branch offset differently, and
the Darwin assembler appears to prefer the "long" form for direct branches.  Thus, in the name of bitwise
equivalence, provide encoding and fixup support for it.

llvm-svn: 121710

llvm-svn: 121709

llvm-svn: 121708

llvm-svn: 121677

llvm-svn: 121656

llvm-svn: 121652

MBlaze delay slot filler was not capable of using ADDK and variants to fill delay slots. This broke several test cases when 121649 was committed. This fixes the regression.

llvm-svn: 121650