- Dec 17, 2012
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Craig Topper authored
Remove EFLAGS from the BLSI/BLSMSK/BLSR patterns. The nodes created by DAG combine don't contain an EFLAGS def. llvm-svn: 170308
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Craig Topper authored
Simplify BMI ANDN matching to use patterns instead of a DAG combine. Also add ANDN to isDefConvertible. llvm-svn: 170305
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Craig Topper authored
llvm-svn: 170304
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Craig Topper authored
Remove store forms of DEC/INC from isDefConvertible. Since they are stores they don't have a register def. llvm-svn: 170303
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Bill Schmidt authored
incompatibility with how complex values are returned. It is sufficient to flag all complex types as direct rather than indirect. A new test case is provided that checks correct IR generation for the various supported flavors of _Complex. llvm-svn: 170302
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Chandler Carruth authored
PR14478 highlights a serious problem in SROA that simply wasn't being exercised due to a lack of vector input code mixed with C-library function calls. Part of SROA was written carefully to handle subvector accesses via memset and memcpy, but the rewriter never grew support for this. Fixing it required refactoring the subvector access code in other parts of SROA so it could be shared, and then fixing the splat formation logic and using subvector insertion (this patch). The PR isn't quite fixed yet, as memcpy is still broken in the same way. I'm starting on that series of patches now. Hopefully this will be enough to bring the bullet benchmark back to life with the bb-vectorizer enabled, but that may require fixing memcpy as well. llvm-svn: 170301
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Chandler Carruth authored
No functionality changed. Another step of refactoring toward solving PR14487. llvm-svn: 170300
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Chandler Carruth authored
No functionality changed. Refactoring leading up to the fix for PR14478 which requires some significant changes to the memset and memcpy rewriting. llvm-svn: 170299
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Craig Topper authored
llvm-svn: 170298
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Nico Weber authored
llvm-svn: 170297
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- Dec 16, 2012
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Dmitri Gribenko authored
llvm-svn: 170296
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Richard Osborne authored
llvm-svn: 170295
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Dmitri Gribenko authored
llvm-svn: 170294
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Richard Osborne authored
llvm-svn: 170293
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Richard Osborne authored
Currently there is no instruction encoding info and XCoreDisassembler::getInstruction() always returns Fail. I intend to add instruction encodings and tests in follow on commits. llvm-svn: 170292
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Richard Osborne authored
llvm-svn: 170291
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Richard Osborne authored
llvm-svn: 170290
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Richard Osborne authored
llvm-svn: 170289
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Richard Osborne authored
This change adds XCoreMCInstLower to do the lowering to MCInst and XCoreInstPrinter to print the MCInsts. llvm-svn: 170288
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Richard Osborne authored
llvm-svn: 170286
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Dmitri Gribenko authored
from some other unrelated header. Patch by Kai. llvm-svn: 170284
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Dmitri Gribenko authored
This enables us to use the same document structure as in other files. llvm-svn: 170283
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Craig Topper authored
Don't use SourceLineCache in getColumnNumber if LastLineNoResult is past the end of the cache. Fixes PR14570. llvm-svn: 170281
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NAKAMURA Takumi authored
llvm-svn: 170280
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Reed Kotler authored
Mips16 is really a processor decoding mode (ala thumb 1) and in the same program, mips16 and mips32 functions can exist and can call each other. If a jal type instruction encounters an address with the lower bit set, then the processor switches to mips16 mode (if it is not already in it). If the lower bit is not set, then it switches to mips32 mode. The linker knows which functions are mips16 and which are mips32. When relocation is performed on code labels, this lower order bit is set if the code label is a mips16 code label. In general this works just fine, however when creating exception handling tables and dwarf, there are cases where you don't want this lower order bit added in. This has been traditionally distinguished in gas assembly source by using a different syntax for the label. lab1: ; this will cause the lower order bit to be added lab2=. ; this will not cause the lower order bit to be added In some cases, it does not matter because in dwarf and debug tables the difference of two labels is used and in that case the lower order bits subtract each other out. To fix this, I have added to mcstreamer the notion of a debuglabel. The default is for label and debug label to be the same. So calling EmitLabel and EmitDebugLabel produce the same result. For various reasons, there is only one set of labels that needs to be modified for the mips exceptions to work. These are the "$eh_func_beginXXX" labels. Mips overrides the debug label suffix from ":" to "=." . This initial patch fixes exceptions. More changes most likely will be needed to DwarfCFException to make all of this work for actual debugging. These changes will be to emit debug labels in some places where a simple label is emitted now. Some historical discussion on this from gcc can be found at: http://gcc.gnu.org/ml/gcc-patches/2008-08/msg00623.html http://gcc.gnu.org/ml/gcc-patches/2008-11/msg01273.html llvm-svn: 170279
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Sean Silva authored
The adornment: === Foo === is for titles, not sections. llvm-svn: 170278
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- Dec 15, 2012
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Dmitri Gribenko authored
highlight console output with "code-block:: console", etc. llvm-svn: 170276
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Dmitri Gribenko authored
Patch by Anastasi Voitova with with small fixes by me. llvm-svn: 170275
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Kostya Serebryany authored
[sanitizer] fix a bug that has crept into the sanitizer allocator and caused SEGV on allocations between 1Mb and 2Mb, improve the test llvm-svn: 170274
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Benjamin Kramer authored
We match the pattern "x >= y ? x-y : 0" into "subus x, y" and two special cases if y is a constant. DAGCombiner canonicalizes those so we first have to undo the canonicalization for those cases. The pattern occurs in gzip when the loop vectorizer is enabled. Part of PR14613. llvm-svn: 170273
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Dmitri Gribenko authored
heading underline. llvm-svn: 170272
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Chandler Carruth authored
llvm-svn: 170271
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Chandler Carruth authored
The alloca width is based on the alloc size, not the type size. llvm-svn: 170270
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Chandler Carruth authored
Not all chips targeted by x86_64 have this feature, but a dramatically increasing number do. Specifying a chip-specific tuning parameter will continue to turn the feature on or off as appropriate for that particular chip, but the generic flag should try to achieve the best performance on the most widely available hardware. Today, the number of chips with fast UA access dwarfs those without in the x86-64 space. Note that this also brings LLVM's code generation for this '-march' flag more in line with that of modern GCCs. Reviewed by Dan Gohman. llvm-svn: 170269
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Chandler Carruth authored
llvm-svn: 170268
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NAKAMURA Takumi authored
llvm-svn: 170267
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Jim Ingham authored
Remove the “len” defaulted parameter from CommandReturnObject::AppendMessage, AppendWarning and AppendError. Nobody was using them, and it meant if you accidentally used the AppendWarning when you meant AppendWarningWithFormat with an integer in the format string, it would compile and then return your string plus some unknown amount of junk. llvm-svn: 170266
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rdar://problem/11990131Greg Clayton authored
Memory read's "repeat" behavior forgets "-t" option. It also formatted the type as hex bytes + ASCII. Now we revert to the default format when displaying types unless the user sets the format option manually. llvm-svn: 170265
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rdar://problem/12156204Greg Clayton authored
x/a print wouldn't always reset the word size to the size of a pointer if a previous memory read using x/<gdb-format> had been used that set it to another width. llvm-svn: 170264
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Will Dietz authored
Results in better block placement that helps close the performance gap when making ubsan checks recoverable. llvm-svn: 170263
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