This can happen when widening a virtual register to a super-register
class.

llvm-svn: 156867

There is no need to look at an always null SrcIdx.

llvm-svn: 156866

 - Hopefully fixes PR11600 (untested).

llvm-svn: 156865

llvm-svn: 156864

llvm-svn: 156857

llvm-svn: 156852

-macho to disassemble the last symbol to the end of the section.

llvm-svn: 156850

this gives a speedup of > 80 in a debug build in the test case of PR12825 (php_sha512_crypt_r)

llvm-svn: 156849

Now both SrcReg and DstReg can be sub-registers of the final coalesced
register.

CoalescerPair::setRegisters still rejects such copies because
RegisterCoalescer doesn't yet handle them.

llvm-svn: 156848

llvm-svn: 156847

This feature avoids creating edges in the scheduler's dependence graph
for non-aliasing memory operations according to whichever alias
analysis is available. It has been fully tested in Hexagon. Before
making this default, it needs to be extended to handle multiple
MachineMemOperands, compile time needs more evaluation, and
benchmarking on X86 and ARM is needed.

Patch by Sergei Larin!

llvm-svn: 156842

that has more than one symbol.  The last symbol was not being disassembled to
the end of the section.

llvm-svn: 156840

 - These libraries are only reported by llvm-config when run from a development
   tree.

llvm-svn: 156838

llvm-svn: 156837

check.

llvm-svn: 156836

Many targets always use the same bitwise encoding value for physical
registers in all (or most) instructions. Add this mapping to the
.td files and TableGen'erate the information and expose an accessor
in MCRegisterInfo.

patch by Tom Stellard.

llvm-svn: 156829

Add the MCRegisterInfo to the factories and constructors.

Patch by Tom Stellard <Tom.Stellard@amd.com>.

llvm-svn: 156828

llvm-svn: 156824

minor simplification to code: Ty is already a SCEV type; don't need to run getEffectiveSCEVType() twice

llvm-svn: 156823

llvm-svn: 156819

llvm-svn: 156815

llvm-svn: 156812

llvm-svn: 156810

llvm-svn: 156808

SelectionDAGBuilder::Clusterify : main functinality was replaced with CRSBuilder::optimize, so big part of Clusterify's code was reduced.

llvm-svn: 156804

resolved.

llvm-svn: 156801

Besides the weight, we also want to store up to two root registers per
unit. Most units will have a single root, the leaf register they
represent. Units created for ad hoc aliasing get two roots: The two
aliasing registers.

The root registers can be used to compute the set of overlapping
registers.

llvm-svn: 156792

llvm-svn: 156791

The purpose of this option is to silence error messages issued by machine
verifier passes and enable them to run to the end. If this option is not
provided, -verify-machineinstrs complains when it discovers there is a
non-terminator instruction (an instruction that is in a delay slot) after the
first terminator in a basic block.

llvm-svn: 156790

llvm-svn: 156787

llvm-svn: 156785

Found by GCC's maybe-uninitialized.

llvm-svn: 156780

This should unbreak llvm-x86_64-linux.

llvm-svn: 156778

RAFast must add an <imp-def> operand when it is rewriting a sub-register
def that isn't a read-modify-write.

llvm-svn: 156777

so that it can be reused in MemCpyOptimizer.  This analysis is needed to remove
an unnecessary memcpy when returning a struct into a local variable.
rdar://11341081
PR12686

llvm-svn: 156776

llvm-svn: 156775

llvm-svn: 156774

llvm-svn: 156772

llvm-svn: 156770

Returning a temporary BitVector is very expensive. If you must, create
the temporary explicitly: Use BitVector(A).flip() instead of ~A.

llvm-svn: 156768