DwarfDebug class could generate the same (inlined) DIVariable twice:
1) when trying to find abstract debug variable for a concrete inlined instance.
2) when explicitly collecting info for variables that were optimized out.

This change makes sure that this duplication won't happen and makes
Clang pass "gdb.opt/inline-locals" test from gdb testsuite.

Reviewed by Eric Christopher.

llvm-svn: 159811

llvm-svn: 159806

llvm-svn: 159804

   Mips specific inline asm operand modifier D.
   
   Comment changes and predicate change.
   
   

llvm-svn: 159802

types.

llvm-svn: 159801

llvm-svn: 159800

llvm-svn: 159789

   
   Print the second half of a double word operand.
   
   The include list was cleaned up a bit as well.
   
   Also the test case was modified to test for both
   big and little patterns.
   

llvm-svn: 159787

Fix an overzealous assertion.  It is legitimate for a target to have multiple fixups on a single instruction that target the same byte, so long as their bit-offsets are coordinates appropriately.

llvm-svn: 159785

llvm-svn: 159771

mips32 rev1 (the directives are emitted when target is mips32r2 too).

llvm-svn: 159770

AsmParser::ParseStatement.

Patch by Vladimir Medic.

llvm-svn: 159768

llvm-svn: 159758

vector erase. No functionality changed.

llvm-svn: 159746

the key -- they are now stored in an IntervalMap.

I noticed this while looking into PR12652.

llvm-svn: 159745

hash_value overload for MachineOperands. This addresses a FIXME
sufficient for me to remove it, and cleans up the code nicely too.

The important changes to the hashing logic:
- TargetFlags are now included in all of the hashes. These were complete
  missed.
- Register operands have their subregisters and whether they are a def
  included in the hash.
- We now actually hash all of the operand types. Previously, many
  operand types were simply *dropped on the floor*. For example:
  - Floating point immediates
  - Large integer immediates (>64-bit)
  - External globals!
  - Register masks
  - Metadata operands
- It removes the offset from the block-address hash; I'm a bit
  suspicious of this, but isIdenticalTo doesn't consider the offset for
  black addresses.

Any patterns involving these entities could have triggered extreme
slowdowns in MachineCSE or PHIElimination. Let me know if there are PRs
you think might be closed now... I'm looking myself, but I may miss
them.

llvm-svn: 159743

corresponding clang warning.

llvm-svn: 159742

broken. This patch fixes the superficial problems which lead to the
intractably slow compile times reported in PR13225.

The specific issue is that we were failing to include the *offset* of
a global variable in the hash code. Oops. This would in turn cause all
MIs which were only distinguishable due to operating on different
offsets of a global variable to produce identical hash functions. In
some of the test cases attached to the PR I saw hash table activity
where there were O(1000) probes-per-lookup *on average*. A very few
entries were responsible for most of these probes.

There is still quite a bit more to do here. The ad-hoc layering of data
in MachineOperands makes them *extremely* brittle to hash correctly.
We're missing quite a few other cases, the only ones I've fixed here are
the specific MO types which were allowed through the assert() in
getOffset().

llvm-svn: 159741

booleans.  Patch by James Benton.

llvm-svn: 159739

[tsan] fix compile-time falilure found while building Chromium with tsan (tsan issue #3). A unit test will follow separately.

llvm-svn: 159736

change.

Move the "Not profitable, avoid CSE!" debug message next to where we fail the
check for profitability and use a different message for avoiding CSE due to
being in different register classes.

llvm-svn: 159729

Function argument and return value registers aren't part of the
encoding, so they should be implicit operands.

llvm-svn: 159728

Also allow trailing register mask operands on non-variadic both
MachineSDNodes and MachineInstrs.

The extra physreg RegisterSDNode operands are added to the MI as
<imp-use> operands. This makes it possible to have non-variadic call
instructions.

Call and return instructions really are non-variadic, the argument
registers should only be used implicitly - they are not part of the
encoding.

llvm-svn: 159727

llvm-svn: 159726

Find the kill as the last terminator to read SrcReg.

Patch by Philipp Brüschweiler!

llvm-svn: 159722

The CopyToReg nodes that set up the argument registers before a call
must be glued to the call instruction. Otherwise, the scheduler may emit
the physreg copies long before the call, causing long live ranges for
the fixed registers.

Besides disabling good register allocation, that can also expose
problems when EmitInstrWithCustomInserter() splits a basic block during
the live range of a physreg.

llvm-svn: 159721

llvm-svn: 159720

159509 and 159479 are reverted. It would be really nice to be able to run
just the coalescer :-(

llvm-svn: 159715

llvm-svn: 159707

Optimized diff operation: implemented the case when LHS and RHS subsets contains single numbers only.

llvm-svn: 159704

  IntegersSubsetMapping
  - Replaced type of Items field from std::list with std::map. In neares future I'll test it with DenseMap and do the correspond replacement
    if possible.

llvm-svn: 159703

llvm-svn: 159701

from IfConversion.cc), and fix some spelling and grammar in the surrounding
prose.

llvm-svn: 159699

Implement the TII hooks needed by EarlyIfConversion to create cmov
instructions and estimate their latency.

Early if-conversion is still not enabled by default.

llvm-svn: 159695

This pass performs if-conversion on SSA form machine code by
speculatively executing both sides of the branch and using a cmov
instruction to select the result. This can help lower the number of
branch mispredictions on architectures like x86 that don't have
predicable instructions.

The current implementation is very aggressive, and causes regressions on
mosts tests. It needs good heuristics that have yet to be implemented.

llvm-svn: 159694

Thanks Duncan for the idea

llvm-svn: 159687

These give quite a bit more information about the DebugInfo and makes it more
readable.

llvm-svn: 159680

(LLVM optimizers cannot do this optimization by themselves)

llvm-svn: 159668

Unfortunately this change requires the cache map to hold WeakVHs instead

llvm-svn: 159667

llvm-svn: 159666