isn't cluttered with things like "Llabel47:Llabel48:  movq  (%rsi), %xmm3"

llvm-svn: 90638

llvm-svn: 90637

instead of SelectionDAGISel.cpp.

llvm-svn: 90636

MachineBasicBlock::canFallThrough(), which is target-independent and more
thorough.

llvm-svn: 90634

llvm-svn: 90633

and that Instruction only. Implement this by setting the "current debug position"
back to Unknown after processing each instruction.

llvm-svn: 90632

Don't print "SrcLine"; just print the filename and line number, which
is obvious enough and more informative.

llvm-svn: 90631

the column number if it is not known. Handle the case of a missing filename
better.

llvm-svn: 90630

llvm-svn: 90621

llvm-svn: 90617

Use new interfaces to print spill size.

llvm-svn: 90611

llvm-svn: 90575

llvm-svn: 90567

llvm-svn: 90566

architectures that LLVM targets, because they don't use this code.

llvm-svn: 90564

The coalescer is supposed to clean these up, but when setting up parameters
for a function call, there may be copies to physregs. If the defining
instruction has been LICM'ed far away, the coalescer won't touch it.

The register allocation hint does not always work - when the register
allocator is backtracking, it clears the hints.

This patch takes care of a few more cases that r90163 missed.

llvm-svn: 90502

- If the reaching definition is an undef and the use is a PHI, add the implicit_def to the end of the source block.
- When reaching value is replaced with another, update the cache as well.

llvm-svn: 90501

Insert composite type DIE into the map before processing type fields. This allows fields to find their context DIE from the map.

llvm-svn: 90498

llvm-svn: 90489

llvm-svn: 90488

Pointed out by Javier Martinez (who also provided a patch).  Since
this logic is not used on (for example) x86, I guess nobody noticed.
Tested by generating SHL, SRL, SRA on various choices of i64 for all
possible shift amounts, and comparing with gcc.  Since I did this on
x86-32, I had to force the use of ExpandShiftWithUnknownAmountBit.
What I'm saying here is that I don't have a testcase I can add to the
repository.

llvm-svn: 90482

llvm-svn: 90481

llvm-svn: 90474

llvm-svn: 90432

Don't pull vector sext through both hands of a logical operation, since doing so prevents the fusion of vector sext and setcc into vsetcc.
Add a testcase for the above transformation.
Fix a bogus use of APInt noticed while tracking this down.

llvm-svn: 90423

llvm-svn: 90415

llvm-svn: 90395

The MO reference to a MachineOperand can be invalidated by
MachineInstr::addOperand. Don't even use it for debugging.

llvm-svn: 90381

Emit method definition DIE at module level (even for methods with inlined functino body at soure level) so that the debugger can invoke it. This fixes many test failures in gdb test suite.

llvm-svn: 90375

Patch by Howard Hinnant!

llvm-svn: 90365

llvm-svn: 90354

llvm-svn: 90353

llvm-svn: 90337

No functionality change.

llvm-svn: 90336

llvm-svn: 90326

llvm-svn: 90318

llvm-svn: 90281

- A valno should be set HasRedefByEC if there is an early clobber def in the middle of its live ranges. It should not be set if the def of the valno is defined by an early clobber.
- If a physical register def is tied to an use and it's an early clobber, it just means the HasRedefByEC is set since it's still one continuous live range.
- Add a couple of missing checks for HasRedefByEC in the coalescer. In general, it should not coalesce a vr with a physical register if the physical register has a early clobber def somewhere. This is overly conservative but that's the price for using such a nasty inline asm "feature".

llvm-svn: 90269

framework omits differentiated edge sources in the case where the labels
are empty strings.

llvm-svn: 90254

llvm-svn: 90253