unpredicated. That is, turn
 subeq  r0, r1, #1
 addne  r0, r1, #1                                                                                                                                                                                                     
into
 sub    r0, r1, #1
 addne  r0, r1, #1

For targets where conditional instructions are always executed, this may be
beneficial. It may remove pseudo anti-dependency in out-of-order execution
CPUs. e.g.
 op    r1, ...
 str   r1, [r10]        ; end-of-life of r1 as div result
 cmp   r0, #65
 movne r1, #44  ; raw dependency on previous r1
 moveq r1, #12

If movne is unpredicated, then
 op    r1, ...
 str   r1, [r10]
 cmp   r0, #65
 mov   r1, #44  ; r1 written unconditionally
 moveq r1, #12

Both mov and moveq are no longer depdendent on the first instruction. This gives
the out-of-order execution engine more freedom to reorder them.

This has passed entire LLVM test suite. But it has not been enabled for any ARM
variant pending more performance evaluation.

rdar://8951196

llvm-svn: 146914

llvm-svn: 146913

llvm-svn: 146912

rdar://problem/10577182
Audit lldb API impl for places where we need to perform a NULL check

Add NULL checks for SBCommandReturnObject.AppendMessage().

llvm-svn: 146911

llvm-svn: 146910

rdar://problem/10577182
Audit lldb API impl for places where we need to perform a NULL check

Add NULL checks for SBCommandInterpreter APIs.

llvm-svn: 146909

Fix PR5279 - don't sliently drop alignment information on stores of types that have alignment less than the natural alignment of the type when it comes from a typedef.

llvm-svn: 146908

llvm-svn: 146907

llvm-svn: 146906

format. It's no longer being used, now that we have a new
implementation of redeclaration chains.

llvm-svn: 146905

But, warn too. // rdar://10597832

llvm-svn: 146904

(more general) fix-up of definition data pointers.

llvm-svn: 146903

<rdar://problem/10596340>

llvm-svn: 146902

llvm-svn: 146901

patterns emit a single LUi instruction instead of a pair of LUi and ORi.

llvm-svn: 146900

rdar://problem/10577182
Audit lldb API impl for places where we need to perform a NULL check

Add NULL checks for SBModule and SBSection APIs.

llvm-svn: 146899

llvm-svn: 146898

llvm-svn: 146897

llvm-svn: 146896

rdar://10602276

llvm-svn: 146895

llvm-svn: 146894

direct-object emitter should emit the appropriate shift instruction depending
on the shift amount.

llvm-svn: 146893

llvm-svn: 146892

"id" from being found by the parser as an
externally-defined type.  Before, "id" would
sometimes make it through if it was defined in
a namespace, but this sometimes caused
confusion, for example when it conflicted with
std::locale::id.

llvm-svn: 146891

llvm-svn: 146890

llvm-svn: 146889

This change reduces the number of instructions generated.

For example, 
(load (add (sub $n0, $n1), (MipsLo got(s))))

results in the following sequence of instructions:
1. sub $n2, $n0, $n1
2. lw got(s)($n2)

Previously, three instructions were needed.
1. sub $n2, $n0, $n1
2. addiu $n3, $n2, got(s)
3. lw 0($n3)

llvm-svn: 146888

llvm-svn: 146887

with a definition pointer (e.g., C++ and Objective-C classes), zip
through the redeclaration chain to make sure that all of the
declarations point to the definition data. 

As part of this, realized again why the first redeclaration of an
entity in a file is important, and brought back that idea.

llvm-svn: 146886

llvm-svn: 146885

There's more variation that we need to handle. Error checking will need
to be on operand predicates.

llvm-svn: 146884

redeclaration templates (RedeclarableTemplateDecl), similarly to the
way (de-)serialization is implemented for Redeclarable<T>. In the
process, found a simpler formulation for handling redeclaration
chains and implemented that in both places.

The new test establishes that we're building the redeclaration chains
properly. However, the FIXME indicates where we're tickling a
different bug that has to do with us not setting the DefinitionData
pointer properly in redeclarations that we detected after the
definition itself was deserialized. The (separable) fix for that bug
is forthcoming.

llvm-svn: 146883

llvm-svn: 146882

llvm-svn: 146881

Add the new TableGen register class synthesizer feature to the release
notes.

llvm-svn: 146875

Now that getMatchingSuperRegClass() returns accurate results, it can be
used to compute constraints imposed by instructions using a sub-register
of a virtual register.

This means we can recompute the register class of any virtual register
by combining the constraints from all its uses.

llvm-svn: 146874

Use information computed while inferring new register classes to emit
accurate, table-driven implementations of getMatchingSuperRegClass().

Delete the old manual, error-prone implementations in the targets.

llvm-svn: 146873

Teach TableGen to create the missing register classes needed for
getMatchingSuperRegClass() to return maximal results.  The function is
still not auto-generated, so it still returns inexact results.

This produces these new register classes:

ARM:
    QQPR_with_dsub_0_in_DPR_8
    QQQQPR_with_dsub_0_in_DPR_8
X86:
    GR64_with_sub_32bit_in_GR32_NOAX
    GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOSP
    GR64_with_sub_16bit_in_GR16_NOREX
    GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX
    GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX
    GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX_NOSP
    GR64_TCW64_and_GR64_with_sub_32bit_in_GR32_NOAX
    GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX
    GR64_with_sub_32bit_in_GR32_TC
    GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_NOAX
    GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_TC
    GR64_with_sub_32bit_in_GR32_AD
    GR64_with_sub_32bit_in_GR32_AD_and_GR32_NOAX

The other targets in the tree are not weird enough to be affected.

llvm-svn: 146872

llvm-svn: 146871

imported modules that don't introduce any new entities of a particular
kind. Allow these entries to be replaced with entries for another
loaded module.

In the included test case, selectors exhibit this behavior.

llvm-svn: 146870