register destinations that are tied to source operands.  The
TargetInstrDescr::findTiedToSrcOperand method silently fails for inline
assembly.  The existing MachineInstr::isRegReDefinedByTwoAddr was very
close to doing what is needed, so this revision makes a few changes to
that method and also renames it to isRegTiedToUseOperand (for consistency
with the very similar isRegTiedToDefOperand and because it handles both
two-address instructions and inline assembly with tied registers).

llvm-svn: 68714

llvm-svn: 61390

instead of requiring all "short description" strings to begin with
two spaces. This makes these strings less mysterious, and it fixes
some cases where short description strings mistakenly did not
begin with two spaces.

llvm-svn: 57521

isReg, etc., from isRegister, etc.

llvm-svn: 57006

llvm-svn: 55779

Keep RegAllocSimple in sync.

llvm-svn: 53351

with RegAllocLocal.

llvm-svn: 53347

with extra checks.

llvm-svn: 53344

adding <map> to many files that actually do need it.

llvm-svn: 48667

llvm-svn: 46930

Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.

llvm-svn: 45695

that it is cheap and efficient to get.

Move a variety of predicates from TargetInstrInfo into 
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around.  Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.

Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.

llvm-svn: 45674

llvm-svn: 45484

that "machine" classes are used to represent the current state of
the code being compiled.  Given this expanded name, we can start 
moving other stuff into it.  For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.

Update all the clients to match.

This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.

llvm-svn: 45467

llvm-svn: 45418

the stored register is killed.

llvm-svn: 44600

llvm-svn: 36662

Due to darwin gcc bug, one version of darwin linker coalesces
static const int, which defauts PassID based pass identification.

llvm-svn: 36652

llvm-svn: 36632

llvm-svn: 36452

llvm-svn: 32698

llvm-svn: 32366

llvm-svn: 32353

llvm-svn: 32321

is 'unsigned'.

llvm-svn: 32279

llvm-svn: 31985

llvm-svn: 31364

Two-address instructions no longer have to be A := A op C. Now any pair of dest / src operands can be tied together.

llvm-svn: 31363

actually *removes* one of the operands, instead of just assigning both operands
the same register.  This make reasoning about instructions unnecessarily complex,
because you need to know if you are before or after register allocation to match
up operand #'s with the target description file.

Changing this also gets rid of a bunch of hacky code in various places.

This patch also includes changes to fold loads into cmp/test instructions in
the X86 backend, along with a significant simplification to the X86 spill
folding code.

llvm-svn: 30108

llvm-svn: 29911

llvm-svn: 29471

llvm-svn: 29434

llvm-svn: 29250

llvm-svn: 29220

llvm-svn: 28973

llvm-svn: 28102

llvm-svn: 25515

code.  PrologEpilogInserter hasn't been updated yet though, so targets cannot
use this info.

llvm-svn: 23536

llvm-svn: 21439

llvm-svn: 21420