"On ARMv6T2 this turns cttz into rbit, clz instead of the 4 instruction
 sequence it is now."

llvm-svn: 93758

clear what information these functions are actually using.

This is also a micro-optimization, as passing a SDNode * around is
simpler than passing a { SDNode *, int } by value or reference.

llvm-svn: 92564

llvm-svn: 91555

between BR_JTr and STREXD.

llvm-svn: 91339

llvm-svn: 91333

llvm-svn: 91329

llvm-svn: 91327

llvm-svn: 91313

llvm-svn: 91307

llvm-svn: 91305

llvm-svn: 91284

just issues an error for the moment. The front end won't yet generate these
intrinsics for ARM, so this is behind the scenes until complete.

llvm-svn: 91200

memory barrier instructions by definition have side effects. This prevents the post-RA scheduler from moving them around.

llvm-svn: 91150

llvm-svn: 91140

llvm-svn: 91090

llvm-svn: 91053

Add memory barrier intrinsic support for ARM. Moving towards adding the atomic operations intrinsics.

llvm-svn: 91003

llvm-svn: 90141

than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.

This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).

llvm-svn: 89720

Note that "hasDotLocAndDotFile"-style debug info was already broken;
people wanting this functionality should implement it in the
AsmPrinter/DwarfWriter code.

llvm-svn: 89711

fold immediate of a + Const into the user as a subtract if it can fit as a negated two-part immediate.

llvm-svn: 89694

llvm-svn: 89478

llvm-svn: 89214

distinguish between them and the more generic instructions (add, mov, and ldr).

llvm-svn: 89108

0b1110 (ALways).  This is so that the disassembler decoder can distinguish among
BX_RET, BRIND, and BXr9.

llvm-svn: 89000

llvm-svn: 86494

llvm-svn: 86404

was wrong and too aggressive in the sense that DPSoRegFrm includes both constant
shifts (with Inst{4} = 0) and register controlled shifts (with Inst{4} = 1 and
Inst{7} = 0).  The 'rr' fragment of the multiclass definitions actually means
register/register with no shift, see A8-11.

llvm-svn: 86319

llvm-svn: 85824

llvm-svn: 85809

clang/test/CodeGen/indirect-goto.c runs! (unoptimized)

llvm-svn: 85577

opcode and operand with a tab.  Check for these instructions in the usual
places.

llvm-svn: 85411

llvm-svn: 85355

llvm-svn: 85299

BL_pred and BLr9_pred.

llvm-svn: 85297

instruction format that already takes care of setting this.

llvm-svn: 85280

for the r/rr fragment of the multiclass AI_unary_rrot/AI_bin_rrot.

llvm-svn: 85271

llvm-svn: 85178

bits.  Johnny, please review -- I do not have a good track record of getting
these right.

llvm-svn: 85173

bits.  Patch by Johnny Chen.

llvm-svn: 85167