llvm-svn: 148578

This is similar to implicit register operands.  MC doesn't understand
register liveness and call clobbers.

llvm-svn: 148437

llvm-svn: 148400

When set, this bit indicates that a register is completely defined by
the value of its sub-registers.

Use the CoveredBySubRegs property to infer which super-registers are
call-preserved given a list of callee-saved registers.  For example, the
ARM registers D8-D15 are callee-saved.  This now automatically implies
that Q4-Q7 are call-preserved.

Conversely, Win64 callees save XMM6-XMM15, but the corresponding
YMM6-YMM15 registers are not call-preserved because they are not fully
defined by their sub-registers.

llvm-svn: 148363

Removing unused default switch cases in switches over enums that already account for all enumeration values explicitly.

(This time I believe I've checked all the -Wreturn-type warnings from GCC & added the couple of llvm_unreachables necessary to silence them. If I've missed any, I'll happily fix them as soon as I know about them)

llvm-svn: 148262

llvm-svn: 147924

llvm-svn: 147923

llvm-svn: 147738

llvm-svn: 147676

llvm-svn: 147541

llvm-svn: 147519

  versions derive from them.
- JALR64 is not needed since N64 does not emit jal. 
- Add template parameter to BranchLink that sets the rt field. 
- Fix the set of temporary registers for O32 and N64.

llvm-svn: 147518

is Mips64.

llvm-svn: 147516

llvm-svn: 147383

Implement encoder methods getJumpTargetOpValue and getBranchTargetOpValue
for jmptarget and brtarget Mips tablegen operand types in the code emitter
for old-style JIT. Rename the pc relative relocation for branches - new
name is Mips::reloc_mips_pc16.

Patch by Sasa Stankovic

llvm-svn: 147382

loadRegFromStackSlot. 

llvm-svn: 147235

llvm-svn: 147234

llvm-svn: 147232

llvm-svn: 147133

ELF relocations.

Patch by Jack Carter.

llvm-svn: 147118

avoid including ADT/Triple.h in many places when the target specific bits are
moved.

llvm-svn: 147059

The patch and test case were originally written by Mans Rullgard.

llvm-svn: 147024

case for DCLO and DCLZ.

llvm-svn: 147022

llvm-svn: 147021

llvm-svn: 147019

DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces
64-bit bswap with a DSBH and DSHD pair.

llvm-svn: 147017

instruction supported by mips32r2, and add a pattern which replaces bswap with
a ROTR and WSBH pair.
 
WSBW is removed since it is not an instruction the current architectures
support.

llvm-svn: 147015

llvm-svn: 147014

llvm-svn: 147013

llvm-svn: 147012

nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU
nodes.

llvm-svn: 147008

llvm-svn: 147007

llvm-svn: 147005

llvm-svn: 147004

llvm-svn: 147003

only when the target ABI is N64.

llvm-svn: 147001

MIPS64 can generate constant +0.0 with a single DMTC1 instruction. 

llvm-svn: 146999

llvm-svn: 146996

llvm-svn: 146995

only when the target ABI is N64. 

llvm-svn: 146992