llvm-svn: 104628

Mon Ping provided; unfortunately bugpoint failed to
reduce it, but I think it's important to have a test for
this in the suite.  8023512.

llvm-svn: 104624

(oye, a word which should be better known to people writing tree
traversals, means grandchild.)

llvm-svn: 104619

llvm-svn: 104574

llvm-svn: 104572

llvm-svn: 104560

This fixes recent regression in store.exp from gdb testsuite.

llvm-svn: 104524

is first emitted, and StackOffsets are emitted in 16 bits.

llvm-svn: 104488

llvm-svn: 104463

llvm-svn: 104421

Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.

llvm-svn: 104419

llvm-svn: 104414

llvm-svn: 104412

llvm-svn: 104410

Evan please verify!

llvm-svn: 104408

Allow machine cse to cse instructions which define physical registers. Controlled by option -machine-cse-phys-defs.

llvm-svn: 104385

so that it will continue to test what it was meant to test when I commit a
separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon.
Fix a DAG combiner crash exposed by this test change.

llvm-svn: 104380

that are aliases of the specified register.
- Rename modifiesRegister to definesRegister since it's looking a def of the
specific register or one of its super-registers. It's not looking for def of a
sub-register or alias that could change the specified register.
- Added modifiesRegister to look for defs of aliases.

llvm-svn: 104377

reads or writes a register.

This takes partial redefines and undef uses into account.

Don't actually use it yet. That caused miscompiles.

llvm-svn: 104372

llvm-svn: 104338

llvm-svn: 104325

This reverts r104322. I think it was causing miscompilations.

llvm-svn: 104323

This correctly handles partial redefines and undef uses.

llvm-svn: 104322

definitions of the virtual register.

This happens when spilling the registers produced by REG_SEQUENCE:

%reg1047:5<def>, %reg1047:6<def>, %reg1047:7<def> = VLD3d8 %reg1033, 0, pred:14, pred:%reg0

The rewriter would spill the register multiple times, dead store elimination
tried to keep up, but ended up cutting the branch it was sitting on.

llvm-svn: 104321

<imp-def> operand for the full register. This ensures that the full physical
register is marked live after register allocation.

llvm-svn: 104320

llvm-svn: 104306

llvm-svn: 104302

Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.

llvm-svn: 104293

llvm-svn: 104265

llvm-svn: 104254

Split DbgVariable. Eventually, variable info will be communicated through frame index, or DBG_VALUE instruction, or collection of DBG_VALUE instructions. Plus each DbgVariable may not need a label.

llvm-svn: 104233

pipeline stall. It's useful for targets like ARM cortex-a8. NEON has a lot
of long latency instructions so a strict register pressure reduction
scheduler does not work well.
Early experiments show this speeds up some NEON loops by over 30%.

llvm-svn: 104216

llvm-svn: 104209

llvm-svn: 104197

test/Codegen/ARM/reg_sequence.ll but it doesn't affect the generated code
because the coalescer cleans it up.  Radar 7998853.

llvm-svn: 104185

llvm-svn: 104175

more than one dbg_value instruction. rdar://7759363

llvm-svn: 104174

llvm-svn: 104173

llvm-svn: 104172

A partial redef now triggers a reload if required. Also don't add
<imp-def,dead> operands for physical superregisters.

Kill flags are still treated as full register kills, and <imp-use,kill> operands
are added for physical superregisters as before.

llvm-svn: 104167