llvm-svn: 11818

into a single LEA instruction.  This should improve the code generated for
things like X->A.B.C[12].D.

The bigger benefit is still coming though.  Note that this uses an LEA instruction
instead of an add, giving the register allocator more freedom.  We should probably
never generate ADDri32's.

llvm-svn: 11817

an intermediate register.

llvm-svn: 11816

block into MachineBasicBlock::getFirstTerminator().

This also fixes a bug in the implementation of the above in both
RegAllocLocal and InstrSched, where instructions where added after the
terminator if the basic block's only instruction was a terminator (it
shouldn't matter for RegAllocLocal since this case never occurs in
practice).

llvm-svn: 11748

block we are in might be empty

llvm-svn: 11744

eventually get an assignment due to elimination of PHIs.

llvm-svn: 11743

llvm-svn: 11729

llvm-svn: 11728

Implement cast Type::ULongTy -> double

llvm-svn: 11726

llvm-svn: 11722

use FP instructions.  This reduces the number of instructions inserted in
176.gcc (for example) from 58074 to 101 (it doesn't use much FP, which
is typical).  This reduction speeds up the entire code generator.  In the
case of 176.gcc, llc went from taking 31.38s to 24.78s.  The passes that
sped up the most are the register allocator and the 2 live variable analysis
passes, which sped up 2.3, 1.3, and 1.5s respectively.  The asmprinter
pass also sped up because it doesn't print the instructions in comments :)

Note that this patch is likely to expose latent bugs in machine code passes,
because now basicblock can be empty, where they were never empty before.  I
cleaned out regalloclocal, but who knows about linscan :)

llvm-svn: 11717

switch statements in the constructors and simplifies the
implementation of the getUseType() member function. You will have to
specify defs using MachineOperand::Def instead of MOTy::Def though
(similarly for Use and UseAndDef).

llvm-svn: 11715

Also, make an assertion actually fireable!

llvm-svn: 11713

AFTER the GEP that was emitted.  :(

llvm-svn: 11712

(minor) benefits right now:

1. An extra dummy MOVrr32 is gone.  This move would often be coallesced by
   both allocators anyway.
2. The code now uses the gep_type_iterator to walk the gep, which should future
   proof it a bit.  It still assumes that array indexes are Longs though.

These don't really justify rewriting the code.  The big benefit will come later
though.

llvm-svn: 11710

leave register operands with the same use/def flags as the original
instruction.

llvm-svn: 11709

this should be folded into it.

llvm-svn: 11705

value is a physreg and one is a virtreg.  For this reason, disable copy folding
entirely for physregs.  Also, use the new isMoveInstr target hook which gives us
folding of FP moves as well.

llvm-svn: 11700

llvm-svn: 11576

llvm-svn: 11560

llvm-svn: 11558

llvm-svn: 11556

representation.. duh!

llvm-svn: 11554

llvm-svn: 11552

llvm-svn: 11550

llvm-svn: 11549

bits wide.

llvm-svn: 11548

llvm-svn: 11547

MOVSX, and MOVZX.

llvm-svn: 11546

and DECm{8,16,32} instructions.

llvm-svn: 11545

llvm-svn: 11544

llvm-svn: 11543

llvm-svn: 11541

llvm-svn: 11540

like compares and test's would be the next huge win...

llvm-svn: 11539

llvm-svn: 11538

llvm-svn: 11537

but the memory reference is full sized.

llvm-svn: 11536

llvm-svn: 11531

order in the correct sense!! Arg!

llvm-svn: 11530