This makes it more clear that the symbol is an internal, compiler-generated
name and gives a little more description about its contents.

llvm-svn: 119564

It was mistakenly looking at the pointer type when checking for the size of
global variables.  This is a partial fix for Radar 8673120.

llvm-svn: 119563

functions of ScalarEvolution, in preparation for memoization and
other optimizations.

llvm-svn: 119562

in the MC lowering process.

llvm-svn: 119559

Avoid isel movcc of large immediates when the large immediate is available in a register. These immediates aren't free.

llvm-svn: 119558

to avoid an unneeded dependence.

llvm-svn: 119557

needs to be checked that this won't break LCSSA form.
Change the existing checking method to a more direct one:
rather than seeing if all predecessors belong to the loop,
check that the replacing value is either not in any loop or
is in a loop that contains the phi node.

llvm-svn: 119556

llvm-svn: 119555

instead of in SCEVAddRecExpr's constructor, in preparation for an
upcoming change.

llvm-svn: 119554

llvm-svn: 119551

default ctor with ConstantRange.

llvm-svn: 119550

and xor. The 32-bit move immediates can be hoisted out of loops by machine
LICM but the isel hacks were preventing them.

Instead, let peephole optimization pass recognize registers that are defined by
immediates and the ARM target hook will fold the immediates in.

Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ
instructions if there are multiple uses. This happens when the 'and' is live
out, machine sink would have sinked the computation and that ends up pessimizing
code. The peephole pass would recognize situations where the 'and' can be
toggled to define CPSR and eliminate the comparison anyway.

2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking
important optimizations.

rdar://8663787, rdar://8241368

llvm-svn: 119548

llvm-svn: 119547

llvm-svn: 119546

llvm-svn: 119542

llvm-svn: 119539

llvm-svn: 119538

instructions out of InstCombine and into InstructionSimplify.  While
there, introduce an m_AllOnes pattern to simplify matching with integers
and vectors with all bits equal to one.

llvm-svn: 119536

llvm-svn: 119529

llvm-svn: 119512

Fixes PR8631.

llvm-svn: 119511

 - No immediate use, but maybe someone feels like hacking on it.

llvm-svn: 119510

llvm-svn: 119509

llvm-svn: 119508

hasConstantValue.  I was leery of using SimplifyInstruction
while the IR was still in a half-baked state, which is the
reason for delaying the simplification until the IR is fully
cooked.

llvm-svn: 119494

phi node itself if it occurs in an unreachable basic block.  Protect
against this.  Hopefully this will fix some more buildbots.

llvm-svn: 119493

llvm-svn: 119492

simplified to itself (this can only happen in unreachable blocks).
Change it to return null instead.  Hopefully this will fix some
buildbot failures.

llvm-svn: 119490

SrcMgrDiagHandler, we can improve clang diagnostics for inline asm:
instead of reporting them on a source line of the original line,
we can report it on the correct line wherever the string literal came
from. For something like this:

void foo() {
  asm("push %rax\n"
      ".code32\n");
}

we used to get this: (note that the line in t.c isn't helpful)

t.c:4:7: error: warning: ignoring directive for now
  asm("push %rax\n"
      ^
<inline asm>:2:1: note: instantiated into assembly here
.code32
^

now we get:

t.c:5:8: error: warning: ignoring directive for now
      ".code32\n"
       ^
<inline asm>:2:1: note: instantiated into assembly here
.code32
^

Note that we're pointing to line 5 properly now.

llvm-svn: 119488

cookie argument to the SourceMgr diagnostic stuff.  This cleanly separates
LLVMContext's inlineasm handler from the sourcemgr error handling 
definition, increasing type safety and cleaning things up.

llvm-svn: 119486

llvm-svn: 119485

llvm-svn: 119484

the cookie argument to setDiagHandler

llvm-svn: 119483

llvm-svn: 119482

llvm-svn: 119463

llvm-svn: 119462

should get the submode from the load/store multiple instruction's opcode.

llvm-svn: 119461

instructions have to distinguish between lists of single- and double-precision
registers in order for the ASM matcher to do a proper job. In all other
respects, a list of single- or double-precision registers are the same as a list
of GPR registers.

llvm-svn: 119460

class, uses DominatorTree which is an analysis.  This change moves all of
the tricky hasConstantValue logic to SimplifyInstruction, and replaces it
with a very simple literal implementation.  I already taught users of
hasConstantValue that need tricky stuff to use SimplifyInstruction instead.
I didn't update InlineFunction because the IR looks like it might be in a
funky state at the point it calls hasConstantValue, which makes calling
SimplifyInstruction dangerous since it can in theory do a lot of tricky
reasoning.  This may be a pessimization, for example in the case where
all phi node operands are either undef or a fixed constant.

llvm-svn: 119459

While there, add a note about an inefficiency I noticed.

llvm-svn: 119458