instruction encodings can be excluded during mips16 processing.

This revision fixes the issue raised by Jim Grosbach.

bool hasStandardEncoding() const { return !inMips16Mode(); }

When micromips is added it will be

bool StandardEncoding() const { return !inMips16Mode()&&  !inMicroMipsMode(); }

No additional testing is needed other than to assure that there is no regression
from this patch.

Patch by Reed Kotler.

llvm-svn: 157234

llvm-svn: 155030

Patch by Vladimir Medic. 

llvm-svn: 154935

llvm-svn: 153925

Patch by Vladimir Medic.

llvm-svn: 153924

llvm-svn: 151847

llvm-svn: 151625

reserving a physical register ($gp or $28) for that purpose.

This will completely eliminate loads that restore the value of $gp after every
function call, if the register allocator assigns a callee-saved register, or
eliminate unnecessary loads if it assigns a temporary register. 

example:

.cpload $25       // set $gp.
...
.cprestore 16     // store $gp to stack slot 16($sp).
...
jalr $25          // function call. clobbers $gp.
lw $gp, 16($sp)   // not emitted if callee-saved reg is chosen.
...
lw $2, 4($gp)
...
jalr $25          // function call.
lw $gp, 16($sp)   // not emitted if $gp is not live after this instruction.
...

llvm-svn: 151402

Add a test case to show fewer instructions are needed to load an immediate
with the new way of loading immediates.

llvm-svn: 148908

llvm-svn: 148862

llvm-svn: 147519

  versions derive from them.
- JALR64 is not needed since N64 does not emit jal. 
- Add template parameter to BranchLink that sets the rt field. 
- Fix the set of temporary registers for O32 and N64.

llvm-svn: 147518

llvm-svn: 147232

DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces
64-bit bswap with a DSBH and DSHD pair.

llvm-svn: 147017

llvm-svn: 147004

llvm-svn: 147003

llvm-svn: 146995

patterns emit a single LUi instruction instead of a pair of LUi and ORi.

llvm-svn: 146900

direct-object emitter should emit the appropriate shift instruction depending
on the shift amount.

llvm-svn: 146893

llvm-svn: 146889

llvm-svn: 146232

- Modify lowering of global TLS address nodes.
- Modify isel of ThreadPointer.
- Wrap target global TLS address nodes that are operands of loads with WrapperPIC. 
- Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be
  substituted with other existing nodes.

llvm-svn: 146175

RDHWR. 

llvm-svn: 146101

llvm-svn: 146097

llvm-svn: 146096

llvm-svn: 146086

llvm-svn: 146059

PerformANDCombine and PerformOrCombine aware of them. Test cases are included
too.

llvm-svn: 145853

nodes.

llvm-svn: 144841

llvm-svn: 144840

llvm-svn: 144554

llvm-svn: 144448

llvm-svn: 144372

llvm-svn: 144370

llvm-svn: 144368

llvm-svn: 143994

when shift amount is larger than 32.

llvm-svn: 143990

instruction definitions.

llvm-svn: 143989

llvm-svn: 143988

llvm-svn: 142216