to pass around a struct instead of a large set of individual values.  This
cleans up the interface and allows more information to be added to the struct
for future targets without requiring changes to each and every target.

NV_CONTRIB

llvm-svn: 157479

- Stop creating stack frame objects needed for saving $gp.
- Insert a node that copies the global pointer register to register $gp
  before the call node. This will ensure $gp is valid at the entry of the
  called function.

llvm-svn: 156692

llvm-svn: 156457

Patch by Jack Carter.

llvm-svn: 156295

Patch by Jack Carter.

llvm-svn: 156294

Patch by Jack Carter.

llvm-svn: 156293

Patch by Jack Carter.

llvm-svn: 156292

Patch by Jack Carter.

llvm-svn: 156285

Patch by Jack Carter.

llvm-svn: 156284

Patch by Jack Carter.

llvm-svn: 156283

llvm-svn: 156282

Patch by Jack Carter.

llvm-svn: 156280

from the previous 2 patches.

Patch by Jack Carter.

llvm-svn: 156279

Patch by Jack Carter.

llvm-svn: 156278

non-floating point general registers allow 8 and 16-bit
elements.

Patch by Jack Carter.

llvm-svn: 156277

This moves the logic for selecting a TLS model to a single place,
instead of the previous three (ARM, Mips, and X86 which already
uses this function).

llvm-svn: 156162

Thanks to Andy Gibbs, to report the issue.

llvm-svn: 155287

Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.

llvm-svn: 155188

otherwise expand FNEG during legalization.

llvm-svn: 154546

Invalid operation is signaled if the operand of these instructions is NaN.

llvm-svn: 154545

- FCOPYSIGN nodes that have operands of different types were not handled.
- Different code was generated depending on the endianness of the target.

Additionally, code is added that emits INS and EXT instructions, if they are
supported by target (they are R2 instructions).

llvm-svn: 154540

llvm-svn: 154062

llvm-svn: 154054

types for N32 ABI. Add new test case and update existing ones.

llvm-svn: 154038

types for N32 ABI. Test case will be updated after the patch that fixes
TargetLowering::getPICJumpTableRelocBase is checked in.

llvm-svn: 154036

types for N32 ABI and update test case.

llvm-svn: 154034

types for N32 ABI and update test case.

llvm-svn: 154031

llvm-svn: 153671

MachinePointerInfo when getStore is called to create a node that stores an
argument passed in register to the stack. Without this change, the post RA 
scheduler will fail to discover the dependencies between the stores
instructions and the instructions that load from a structure passed by value. 

The link to the related discussion is here:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-March/048055.html

llvm-svn: 153499

llvm-svn: 153498

Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.

llvm-svn: 152997

llvm-svn: 152538

operation action of nodes.

llvm-svn: 152452

llvm-svn: 152450

llvm-svn: 152290

For example, this pattern 
(select (setcc lhs, rhs, cc), true, 0)
is transformed to this one:
(select (setcc lhs, rhs, inverse(cc)), 0, true)

This enables MipsDAGToDAGISel::ReplaceUsesWithZeroReg (added in r152280) to
replace 0 with $zero.

llvm-svn: 152285

llvm-svn: 152282

llvm-svn: 151847

and stores was added.

- SelectAddr should return false if Parent is an unaligned f32 load or store.
- Only aligned load and store nodes should be matched to select reg+imm
  floating point instructions.
- MIPS does not have support for f64 unaligned load or store instructions.

llvm-svn: 151843

llvm-svn: 151645