llvm-svn: 132624

A TableGen backend can define how certain classes can be expanded into
ordered sets of defs, typically by evaluating a specific field in the
record. The SetTheory class can then evaluate DAG expressions that refer
to these named sets.

A number of standard set and list operations are predefined, and the
backend can add more specialized operators if needed. The -print-sets
backend is used by SetTheory.td to provide examples.

This is intended to simplify how register classes are defined:

  def GR32_NOSP : RegisterClass<"X86", [i32], 32, (sub GR32, ESP)>;

llvm-svn: 132621

llvm-svn: 132537

Some register classes are only used for instruction operand constraints.
They should never be used for virtual registers. Previously, those
register classes were given an empty allocation order, but now you can
say 'let isAllocatable=0' in the register class definition.

TableGen calculates if a register is part of any allocatable register
class, and makes that information available in TargetRegisterDesc::inAllocatableClass.

The goal here is to eliminate use cases for overriding allocation_order_*
methods.

llvm-svn: 132508

llvm-svn: 132395

must be encoded decremented by one. Only add encoding tests for ssat16
because ssat can't be parsed yet.

llvm-svn: 132324

directives.

Fixes PR9826.

llvm-svn: 132317

same dwarf number. This will be used for creating a dwarf number to register
mapping.

The only case that needs this so far is the XMM/YMM registers that unfortunately
do have the same numbers.

llvm-svn: 132314

switch.  With this newfound organization, teach tblgen how not to give
all intrinsics the 'nounwind' attribute.  Introduce a new intrinsic,
llvm.eh.resume, which does not have this attribute.  Documentation and uses
to follow.

llvm-svn: 132252

There was no way to check if a given register/mode pair was valid. We now return
an error code (-2) instead of asserting. If anyone thinks that an assert
at this point  is really needed, we can autogen a hasValidDwarfRegNum instead.

llvm-svn: 132236

-Emit an empty warning option as string ("") instead of 0.
-For diagnostic names also emit the size of the string.

llvm-svn: 132046

operands to an instruction aren't great, so an iterative search is fairly quick
and doesn't have the overhead of std::map.

llvm-svn: 131886

the root if there is only one such node. This leaves only 2 verifier failures in
the entire test suite when running "make check".

llvm-svn: 131677

In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32.
Updated test case and reverted change to the PerfectShuffle Table.

llvm-svn: 131529

vrev is incorrectly defined in the perfect shuffle table. The ordering is backwards (should be 0x3210 versus 0x1032) which exposed a bug when doing a shuffle on a 4xi16. I've attached a test case.

llvm-svn: 131488

Ambiguous sub-register index compositions are OK as long as the backend writer
knows what he is doing.

llvm-svn: 131134

llvm-svn: 131085

The RegisterInfo.td file should only specify the indexes that sources need to
refer to. The rest is inferred.

llvm-svn: 131058

error is detected is a good thing.

llvm-svn: 131005

llvm-svn: 131004

llvm-svn: 130914

not, I'll just add them here and be done with it.

llvm-svn: 130819

llvm-svn: 130779

Filter out pattterns from the FastISel emitter which it doesn't actually know how to handle.  No significant functionality change at the moment, but it's necessary for some changes I'm planning.

llvm-svn: 130547

under cmake).

Add libprofile_rt.a so that we can tell clang to link against it in --coverage
mode. Also turn it on by default in cmake builds.

Oscar, this touches a change you made for EXCLUDE_FROM_ALL support -- I think
I've done the right thing, but please let me know (or fix and commit) if not!

llvm-svn: 130470

Fix a bug in tblgen that caused incorrect encodings on instructions that specified operands with "bit" instead of "bits<1>".
Unfortunately, my only testcase for this is fragile, and the ARM AsmParser can't round trip the instruction in question.
<rdar://problem/9345702>

llvm-svn: 130410

llvm-svn: 130092

llvm-svn: 130068

print out ldr, not ldr.n.

rdar://problem/9267772

llvm-svn: 130008

This is needed so the front-end can see "aligned" attributes on the type
for the pointer arguments.  Radar 9311427.

llvm-svn: 129964

These values were not used for anything. Spill size and alignment is a property
of the register class, not the register.

llvm-svn: 129906

On the x86-64 and thumb2 targets, some registers are more expensive to encode
than others in the same register class.

Add a CostPerUse field to the TableGen register description, and make it
available from TRI->getCostPerUse. This represents the cost of a REX prefix or a
32-bit instruction encoding required by choosing a high register.

Teach the greedy register allocator to prefer cheap registers for busy live
ranges (as indicated by spill weight).

llvm-svn: 129864

true on success and false on failure. Update callers.

llvm-svn: 129722

llvm-svn: 129708

the generated FastISel.  X86 doesn't need to generate code to match ADD16ri8 
since ADD16ri will do just fine.  This is a small codesize win in the generated
instruction selector.

llvm-svn: 129692

value constraints on them (when defined as ImmLeaf's).  This is particularly important
for X86-64, where almost all reg/imm instructions take a i64immSExt32 immediate operand,
which has a value constraint.  Before this patch we ended up iseling the examples into
such amazing code as:

	movabsq	$7, %rax
	imulq	%rax, %rdi
	movq	%rdi, %rax
	ret

now we produce:

	imulq	$7, %rdi, %rax
	ret

This dramatically shrinks the generated code at -O0 on x86-64.

llvm-svn: 129691

No functionality change.

llvm-svn: 129680

since the strings are always exactly one character, and there are usually only 2-3 operands.

llvm-svn: 129678

llvm-svn: 129677

kind of predicate: one that is specific to imm nodes.  The predicate function
specified here just checks an int64_t directly instead of messing around with
SDNode's.  The virtue of this is that it means that fastisel and other things
can reason about these predicates.

llvm-svn: 129675