llvm-svn: 138660

llvm-svn: 138623

llvm-svn: 138592

llvm-svn: 138588

llvm-svn: 138587

Add more missing TB encodings to VEX instructions to allow them to be disassembled. Fixes remainder of PR10678.

llvm-svn: 138553

Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be disassembled. Fixes PR10723.

llvm-svn: 138551

llvm-svn: 138546

llvm-svn: 138545

file, and move more code around!

llvm-svn: 138521

llvm-svn: 138520

llvm-svn: 138519

the missing ones for AVX.

llvm-svn: 138518

llvm-svn: 138517

pattern for 128-bit AVX mode.

llvm-svn: 138516

explicit about which subtarget they refer to, and add AVX versions of
the ones we currently don't. Remove old and now wrong comments!

llvm-svn: 138515

explicit about which subtarget they refer to, and add AVX versions of
the ones we currently don't. Make the mask check more strict, to be
clear it won't be used to match to 256-bit versions!

llvm-svn: 138514

Hook up 64-bit atomic load/store on x86-32.  I plan to write more efficient implementations eventually.

llvm-svn: 138505

llvm-svn: 138487

llvm-svn: 138478

llvm-svn: 138461

These are strictly utilities for registering targets and components.

llvm-svn: 138450

Break 256-bit vector int add/sub/mul into two 128-bit operations to avoid costly scalarization. Fixes PR10711.

llvm-svn: 138427

permutations. Also tidy up some patterns and make them close to their
instruction definition!

llvm-svn: 138392

from MC.

llvm-svn: 138367

llvm-svn: 138354

Add support for breaking 256-bit v16i16 and v32i8 VSETCC into two 128-bit ones, avoiding sclarization. Add vex form of pcmpeqq and pcmpgtq. Fixes more cases for PR10712.

llvm-svn: 138321

SSE transition penalty. The pass is enabled through the "x86-use-vzeroupper"
llc command line option. This is only the first step (very naive and
conservative one) to sketch out the idea, but proper DFA is coming next
to allow smarter decisions. Comments and ideas now and in further commits
will be very appreciated.

llvm-svn: 138317

llvm-svn: 138285

avoding scalarization of the compare. Reduces code from 59 to 6
instructions. Fix PR10712.

llvm-svn: 138271

llvm-svn: 138270

a bug and add a testcase!

llvm-svn: 138123

llvm-svn: 138034

implementation!

llvm-svn: 138029

instead of 2. They were already defined this way in their regular
version, but not for the intrinsics versions (*_Int), and that would work
for assembly emission but not for object code, since a MachineOperand
would be missing. This commit fix PR10697.

Also removed the {VSQRT,VRSQRT,VRCP}r_Int forms and match the intrinsic
via INSERT_SUBREG+EXTRACT_SUBREG patterns. The same couldn't be done for
memory versions because sse_load_f32/sse_load_f64 operand need special
handling and don't work like regular "addr" operands.

There are right now 114 "*_Int" and 98 "Int_*" forms! I'm slowly
removing them as I step through, but hope we can get rid of these
someday, they are really annoying :)

llvm-svn: 138012

v2i64

llvm-svn: 137919

shift amount is variable

llvm-svn: 137885

Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid.  Only used for ARM UNPREDICTABLE instructions at the moment.
Patch by James Molloy.

llvm-svn: 137830

match splats in the form (splat (scalar_to_vector (load ...))) whenever
the load can be folded. All the logic and instruction emission is
working but because of PR8156, there are no ways to match loads, cause
they can never be folded for splats. Thus, the tests are XFAILed, but
I've tested and exercised all the logic using a relaxed version for
checking the foldable loads, as if the bug was already fixed. This
should work out of the box once PR8156 gets fixed since MayFoldLoad will
work as expected.

llvm-svn: 137810

llvm-svn: 137808