llvm-svn: 67668

llvm-svn: 67661

llvm-svn: 67649

the target constraint specifies a specific physreg.

llvm-svn: 67618

llvm-svn: 67617

fail.

llvm-svn: 67616

canClobberPhysRegDefs if the successor node doesn't
clobber any physical registers.

llvm-svn: 67587

help out the register pressure reduction heuristics in the case of
nodes with multiple uses. Currently this uses very conservative
heuristics, so it doesn't have a broad impact, but in cases where it
does help it can make a big difference.

llvm-svn: 67586

llvm-svn: 67580

Fix a bug in spill weight computation. If the alias is a super-register, and the super-register is in the register class we are trying to allocate. Then add the weight to all sub-registers of the super-register even if they are not aliases.                                                                                                  
e.g. allocating for GR32, bh is not used, updating bl spill weight.                                                                                                        
     bl should get the same spill weight otherwise it will be choosen                                                                                              
     as a spill candidate since spilling bh doesn't make ebx available.
This fix PR2866.

llvm-svn: 67574

same as a normal i80 {low64, high16} rather
than its own {high64, low16}.  A depressing number
of places know about this; I think I got them all.
Bitcode readers and writers convert back to the old
form to avoid breaking compatibility.

llvm-svn: 67562

a data dependency on the load node, so it really needs a
data-dependence edge to the load node, even if the load previously
existed.

And add a few comments.

llvm-svn: 67554

llvm-svn: 67544

actually have uses, which reflects the way it's used.

llvm-svn: 67540

in an SUnit, instead of just the first one. This fix is needed
by some upcoming scheduler changes.

llvm-svn: 67531

defs, regardless of whether they are actually used.

llvm-svn: 67528

explicitly flush it.

llvm-svn: 67526

Model inline asm constraint which ties an input to an output register as machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies.

llvm-svn: 67512

Do not fold away subreg_to_reg if the source register has a sub-register index. That means the source register is taking a sub-register of a larger register. e.g. On x86
%RAX<def> = ...
%RAX<def> = SUBREG_TO_REG 0, %EAX:3<kill>, 3
The first def is defining RAX, not EAX so the top bits were not zero-extended.

llvm-svn: 67511

llvm-svn: 67400

For inline asm output operand that matches an input. Encode the input operand index in the high bits.

llvm-svn: 67387

llvm-svn: 67372

llvm-svn: 67370

llvm-svn: 67364

 - Make type declarations match the struct/class keyword of the definition.
 - Move AddSignalHandler into the namespace where it belongs.
 - Correctly call functions from template base.
 - Some other small changes.
With this patch, LLVM and Clang should build properly and with far less noise under VS2008.

llvm-svn: 67347

llvm-svn: 67335

is the first in its block.  This is PR3842.

llvm-svn: 67304

and expanding a bit convert (PR3711).  In both cases, we extract the
valid part of the widen vector and then do the conversion.

llvm-svn: 67175

Some architectures (like x86) don't require it.
This fixes bug 3779.

llvm-svn: 67132

size by the array amount as an i32 value instead of promoting from
i32 to i64 then doing the multiply.  Not doing this broke wrap-around
assumptions that the optimizers (validly) made.  The ultimate real
fix for this is to introduce i64 version of alloca and remove mallocinst.

This fixes PR3829

llvm-svn: 67093

llvm-svn: 67082

(which produces "call L_f$stub" rather than "call f").

llvm-svn: 67079

vector shuffle mask. Forced the mask to be built using i32.  Note: this will
be irrelevant once vector_shuffle no longer takes a build vector for the
shuffle mask.

llvm-svn: 67076

Spiller may unfold load / mod / store instructions as an optimization when the would be loaded value is available in a register. It needs to check if it's legal to clobber the register. Also, the register can contain values of multiple spill slots, make sure to check all instead of just the one being unfolded.

llvm-svn: 67068

U    test/CodeGen/X86/2009-03-13-PHIElimBug.ll
D    test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll
U    lib/CodeGen/PHIElimination.cpp

r67049 was causing this failure:

Running /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/test/CodeGen/X86/dg.exp ...
FAIL: /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/test/CodeGen/X86/2009-03-13-PHIElimBug.ll for PR3784
Failed with exit(1) at line 1
while running:  llvm-as < /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/test/CodeGen/X86/2009-03-13-PHIElimBug.ll |  llc -march=x86 | /usr/bin/grep -A 2 {call f} | /usr/bin/grep movl
child process exited abnormally

llvm-svn: 67051

how invokes are set up.  The fix could be disturbed by
register copies coming after the EH_LABEL, and also didn't
behave quite right when it was the invoke result that
was used in a phi node.  Also (see new testcase) fix
another phi elimination bug while there: register copies
in the landing pad need to come after the EH_LABEL, because
that's where execution branches to when unwinding.  If they
come before the EH_LABEL then they will never be executed...
Also tweak the original testcase so it doesn't use a no-longer
existing counter.
The accumulated phi elimination changes fix two of seven Ada
testsuite failures that turned up after landing pad critical
edge splitting was turned off.  So there's probably more to come.

llvm-svn: 67049

useful with it at the moment, but it will in the future.

llvm-svn: 67012

llvm-svn: 67000

if FPConstant is legal because if the FPConstant doesn't need to be stored
in a constant pool, the transformation is unlikely to be profitable.

llvm-svn: 66994

ptrtoint and inttoptr in X86FastISel. These casts aren't always
handled in the generic FastISel code because X86 sometimes needs
custom code to do truncation and zero-extension.

llvm-svn: 66988