llvm-svn: 106677

llvm-svn: 106671

llvm-svn: 106621

and operand renaming to help.

The giant turn the constraints on and selectively turn it off
should probably be inverted at some point since it's just largely
50/50.

llvm-svn: 106367

the register.  While we're at it, make sure it's in the right one.

llvm-svn: 105645

llvm-svn: 105381

to be matched.

llvm-svn: 104757

llvm-svn: 104731

Use the tablegen-produced enums.

llvm-svn: 104493

MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example:
  addw $0xFFFF, %ax
should match the same as
  addw $-1, %ax
but we used to match it to the longer encoding.

llvm-svn: 104453

llvm-svn: 104452

llvm-svn: 104272

instructions.

llvm-svn: 104231

prefix byte problem as in r104062.
 - As a total hack to keep the TAILCALL markers in the output, which some tests depend on, this invents a new TAILJMP_1 instruction.

llvm-svn: 104120

argument, like "int $4", to not get an Assertion error.

llvm-svn: 103791

llvm-svn: 103778

llvm-svn: 103776

after testing before committing.

llvm-svn: 103681

llvm-svn: 103677

lower them to the correct x86-64 instructions since we 
don't have a clean way to handle this in td files yet.
rdar://7947184

llvm-svn: 103668

part first.  rdar://7947184

llvm-svn: 103660

 - This fixes "leal 0, %eax", for example.

llvm-svn: 103205

and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.

llvm-svn: 103196

caused the a pushl instruction to be incorrectly encoding using only two bytes
of immediate, causing the following 2 instruction bytes to be part of the 32-bit
immediate value.  Also fixed the one byte form of push to be used when the
immediate would fit in a signed extended byte.  Lastly changed the names to not
include the 32 of PUSH32 since they actually push the size of the stack pointer.

llvm-svn: 102951

llvm-svn: 102730

Operand size override prefix to be part of their records.

llvm-svn: 102556

llvm-svn: 102493

Rather than having a ton of patterns for double shift instructions, e.g. SHLD16rrCL, just perform custom dag combine to form x86 specific dag so they match to the same pattern. This also makes sure later dag combine do not cause isel to miss them (e.g. promoting i16 to i32).

llvm-svn: 102485

llvm-svn: 102467

llvm-svn: 101979

llvm-svn: 101621

llvm-svn: 100480

a new subtarget option for AES and check for the support.  Add "westmere"
line of processors and add AES-NI support to the core i7.

Add a couple of TODOs for information I couldn't verify.

llvm-svn: 100231

*input* of other type, which is the VT. 

llvm-svn: 99749

llvm-svn: 99743

nodes all have an EFLAGS result when made by isel lowering.

llvm-svn: 99736

llvm-svn: 99700

llvm-svn: 99686

Remove much horribleness from X86InstrFormats as a result. Similar
simplifications are probably possible for other targets.

llvm-svn: 99539

handles dead implicit results more aggressively.  More
to come, I think this is now just a data entry problem.

llvm-svn: 99486