- Feb 25, 2012
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Akira Hatanaka authored
add/sub instructions. llvm-svn: 151415
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- Feb 24, 2012
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Akira Hatanaka authored
reserving a physical register ($gp or $28) for that purpose. This will completely eliminate loads that restore the value of $gp after every function call, if the register allocator assigns a callee-saved register, or eliminate unnecessary loads if it assigns a temporary register. example: .cpload $25 // set $gp. ... .cprestore 16 // store $gp to stack slot 16($sp). ... jalr $25 // function call. clobbers $gp. lw $gp, 16($sp) // not emitted if callee-saved reg is chosen. ... lw $2, 4($gp) ... jalr $25 // function call. lw $gp, 16($sp) // not emitted if $gp is not live after this instruction. ... llvm-svn: 151402
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Jia Liu authored
llvm-svn: 151341
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Jia Liu authored
llvm-svn: 151340
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Jia Liu authored
llvm-svn: 151337
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Jia Liu authored
llvm-svn: 151332
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- Feb 22, 2012
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Craig Topper authored
Make all pointers to TargetRegisterClass const since they are all pointers to static data that should not be modified. llvm-svn: 151134
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Akira Hatanaka authored
llvm-svn: 151107
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- Feb 19, 2012
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Ahmed Charles authored
llvm-svn: 150918
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- Feb 17, 2012
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Jia Liu authored
llvm-svn: 150805
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Akira Hatanaka authored
instructions to be emitted. llvm-svn: 150782
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Jia Liu authored
llvm-svn: 150775
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- Feb 16, 2012
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Akira Hatanaka authored
llvm-svn: 150739
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Akira Hatanaka authored
llvm-svn: 150706
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- Feb 07, 2012
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Craig Topper authored
llvm-svn: 149961
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- Feb 05, 2012
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Craig Topper authored
llvm-svn: 149814
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- Feb 04, 2012
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Andrew Trick authored
Passes prior to instructon selection are now split into separate configurable stages. Header dependencies are simplified. The bulk of this diff is simply removal of the silly DisableVerify flags. Sorry for the target header churn. Attempting to stabilize them. llvm-svn: 149754
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- Feb 03, 2012
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Andrew Trick authored
Allows command line overrides to be centralized in LLVMTargetMachine.cpp. LLVMTargetMachine can intercept common passes and give precedence to command line overrides. Allows adding "internal" target configuration options without touching TargetOptions. Encapsulates the PassManager. Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs. Allows modifying the target configuration hooks without rebuilding the world. llvm-svn: 149672
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Akira Hatanaka authored
needed to emit a 64-bit gp-relative relocation entry. Make changes necessary for emitting jump tables which have entries with directive .gpdword. This patch does not implement the parts needed for direct object emission or JIT. llvm-svn: 149668
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- Feb 02, 2012
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Akira Hatanaka authored
llvm-svn: 149585
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Akira Hatanaka authored
selector registers. llvm-svn: 149584
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Akira Hatanaka authored
llvm-svn: 149583
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- Jan 28, 2012
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James Molloy authored
Fixes PR11877 llvm-svn: 149180
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- Jan 25, 2012
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Akira Hatanaka authored
llvm-svn: 148918
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Akira Hatanaka authored
- Use MipsAnalyzeImmediate to expand immediates that do not fit in 16-bit. - Change the types of variables so that they are sufficiently large to handle 64-bit pointers. - Emit instructions to set register $28 in a function prologue after instructions which store callee-saved registers have been emitted. llvm-svn: 148917
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Akira Hatanaka authored
expand offsets that do not fit in the 16-bit immediate field of load and store instructions. Also change the types of variables so that they are sufficiently large to handle 64-bit pointers. llvm-svn: 148916
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NAKAMURA Takumi authored
inttypes.h is not supplied in msvc. llvm-svn: 148912
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NAKAMURA Takumi authored
llvm-svn: 148909
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Akira Hatanaka authored
Add a test case to show fewer instructions are needed to load an immediate with the new way of loading immediates. llvm-svn: 148908
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Akira Hatanaka authored
load an immediate. llvm-svn: 148900
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Akira Hatanaka authored
which is what N32/64 does. llvm-svn: 148875
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- Jan 24, 2012
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Akira Hatanaka authored
llvm-svn: 148871
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Akira Hatanaka authored
llvm-svn: 148869
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Akira Hatanaka authored
llvm-svn: 148862
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Owen Anderson authored
Widen the instruction encoder that TblGen emits to a 64 bits, which should accomodate every target I can think of offhand. llvm-svn: 148833
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- Jan 20, 2012
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David Blaikie authored
llvm-svn: 148578
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- Jan 19, 2012
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Jakob Stoklund Olesen authored
This is similar to implicit register operands. MC doesn't understand register liveness and call clobbers. llvm-svn: 148437
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- Jan 18, 2012
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Jim Grosbach authored
llvm-svn: 148400
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Jakob Stoklund Olesen authored
When set, this bit indicates that a register is completely defined by the value of its sub-registers. Use the CoveredBySubRegs property to infer which super-registers are call-preserved given a list of callee-saved registers. For example, the ARM registers D8-D15 are callee-saved. This now automatically implies that Q4-Q7 are call-preserved. Conversely, Win64 callees save XMM6-XMM15, but the corresponding YMM6-YMM15 registers are not call-preserved because they are not fully defined by their sub-registers. llvm-svn: 148363
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- Jan 17, 2012
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David Blaikie authored
Removing unused default switch cases in switches over enums that already account for all enumeration values explicitly. (This time I believe I've checked all the -Wreturn-type warnings from GCC & added the couple of llvm_unreachables necessary to silence them. If I've missed any, I'll happily fix them as soon as I know about them) llvm-svn: 148262
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