mask.

llvm-svn: 48750

llvm-svn: 48749

llvm-svn: 48747

- SSE4.1 extractfps extracts a f32 into a gr32 register. Very useful! Not. Fix the instruction specification and teaches lowering code to use it only when the only use is a store instruction.

llvm-svn: 48746

llvm-svn: 48744

llvm-svn: 48743

llvm-svn: 48740

llvm-svn: 48739

llvm-svn: 48738

llvm-svn: 48736

llvm-svn: 48734

llvm-svn: 48733

llvm-svn: 48732

llvm-svn: 48731

llvm-svn: 48730

llvm-svn: 48729

llvm-svn: 48728

field to store the alignment value instead of haing a
separate field.

llvm-svn: 48727

llvm-svn: 48726

Increasing the inline limit from (overly conservative) 200 to 300. Given each BB costs 20 and each instruction costs 5, 200 means a 4 BB function + 24 instructions (actually less because caller's size also contributes to it).

Furthermore, double the limit when more than 10% of the callee instructions are vector instructions. Multimedia kernels tend to love inlining.

llvm-svn: 48725

llvm-svn: 48723

llvm-svn: 48722

llvm-svn: 48721

llvm-svn: 48720

With this pass, StrongPHIElim can compile very simple testcases correctly.  There's still a ways
to go before it's ready for prime time, though.

llvm-svn: 48719

Transform (zext (or (icmp), (icmp))) to (or (zext (cimp), (zext icmp))) if at least one of the (zext icmp) can be transformed to eliminate an icmp.

llvm-svn: 48715

llvm-svn: 48714

llvm-svn: 48713

llvm-svn: 48712

llvm-svn: 48711

llvm-svn: 48710

llvm-svn: 48709

llvm-svn: 48708

llvm-svn: 48707

llvm-svn: 48706

llvm-svn: 48705

llvm-svn: 48704

llvm-svn: 48703

of compiler used.

llvm-svn: 48702

llvm-svn: 48701