llvm-svn: 104163

occuring on..." which breaks some Objective-C code. Working on getting a test
case...

llvm-svn: 104150

partial redefines.

We are going to treat a partial redefine of a virtual register as a
read-modify-write:

  %reg1024:6 = OP

Unless the register is fully clobbered:

  %reg1024:6 = OP, %reg1024<imp-def>

MachineInstr::readsVirtualRegister() knows the difference. The first case is a
read, the second isn't.

llvm-svn: 104149

llvm-svn: 104148

Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace.

llvm-svn: 104147

lowering REG_SEQUENCE instructions.

Insert copies for REG_SEQUENCE sources not killed to avoid breaking later passes.

llvm-svn: 104146

llvm-svn: 104145

llvm-svn: 104143

llvm-svn: 104142

need to be promoted.  The BUILD_VECTOR and EXTRACT_VECTOR_ELT nodes generated
here already allow the promoted type to be used without further changes, so
just do the promotion.  This fixes part of pr7167.

llvm-svn: 104141

llvm-svn: 104140

some seriously non-linear performance with deeply nested template
instantiations, as shown in PR6998.

llvm-svn: 104139

Remove clang_isDeclarationADefinition() since its functionality is already provided by clang_isCursorDefinition().

llvm-svn: 104138

llvm-svn: 104135

llvm-svn: 104122

llvm-svn: 104121

prefix byte problem as in r104062.
 - As a total hack to keep the TAILCALL markers in the output, which some tests depend on, this invents a new TAILJMP_1 instruction.

llvm-svn: 104120

llvm-svn: 104118

template names. We were completely missing naming classes for many unqualified
lookups, but this didn't trigger code paths that need it. This removes part of
an optimization that re-uses the template name lookup done by the parser to
determine if explicit template arguments actually form a template-id.
Unfortunately the technique for avoiding the duplicate lookup lost needed data
such as the class context in which the lookup succeeded.

llvm-svn: 104117

CALL64pcrel32, for the same reason.

llvm-svn: 104116

t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM.

llvm-svn: 104115

llvm-svn: 104114

llvm-svn: 104113

llvm-svn: 104112

Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects.

llvm-svn: 104111

llvm-svn: 104110

avoid same prefix byte problem as in r104062.

llvm-svn: 104108

way regardless of whether some overloaded operator functions were
found by name lookup within the template. Fixes PR6851.

llvm-svn: 104107

llvm-svn: 104106

llvm-svn: 104105

the same .cpp file as provided the definitions referenced these functions,
hiding the issue. However, they are clearly no longer inline. Let me know if
there is a reason to move their definitions to the header and make them truly
inline.

llvm-svn: 104104

llvm-svn: 104103

Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM.

llvm-svn: 104102

welcome for one.

llvm-svn: 104101

llvm-svn: 104095

Intrinsics which do a vector compare (results are all zero or all ones) are modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction.

The trouble arises when the result of a vector cmp + sext is then and'ed with all ones. Instcombine will turn it into a vector cmp + zext, dag combiner will miss turning it into a vsetcc and hell breaks loose after that.

Teach dag combine to turn a vector cpm + zest into a vsetcc + and 1. This fixes rdar://7923010.

llvm-svn: 104094

opcodes into a helper function. This fixes a few places in the code
which were not properly selecting the 8-bit-immediate opcodes.

llvm-svn: 104091

llvm-svn: 104090

llvm-svn: 104089

constants in registers which partially cancel out their immediate fields.

llvm-svn: 104088