TLOF, unifying all the dwarf targets at the same time.

llvm-svn: 77889

llvm-svn: 77888

the only real caller (GetFunctionSizeInBytes) uses it.

The custom ARM implementation of this is basically reimplementing
an assembler poorly for negligible gain.  It should be removed 
IMNSHO, but I'll leave that to ARMish folks to decide.

llvm-svn: 77877

defaults to being ELF.

llvm-svn: 77866

no longer depends on TM!

llvm-svn: 77863

llvm-svn: 77861

even considering #if 0 code.

llvm-svn: 77856

getLSDASection() to be more specific.  This makes it pretty obvious
that the ELF LSDA section is being specified wrong in PIC mode.  We're
probably getting a lot of startup-time relocations to a readonly page,
which is expensive and bad.

Someone who cares about ELF C++ should investigate this.

llvm-svn: 77847

operands.

llvm-svn: 77837

compute it based on what it knows.  As part of this, rename getSectionForMergeableConstant
to getSectionForConstant because it works for non-mergable constants also.

The only functionality change from this is that Xcore will start dropping
its jump tables into readonly section instead of data section in -static mode.
This should be fine as the linker resolves the relocations.  If this is a
problem, let me know and we'll come up with another solution.

llvm-svn: 77833

llvm-svn: 77820

llvm-svn: 77806

llvm-svn: 77795

llvm-svn: 77768

be more careful about the return value of runOnMachineFunction.

llvm-svn: 77758

llvm-svn: 77757

llvm-svn: 77755

 - Operands which are just a label should be parsed as immediates, not memory
   operands (from the assembler perspective).

 - Match a few more flavors of immediates.

 - Distinguish match functions for memory operands which don't take a segment
   register.

 - We match the .s for "hello world" now!

llvm-svn: 77745

thing is #if0'd out anyway.  Just simplify the code by reducing the interface.
Not deleting this is essential for Bill's continuing happiness.

llvm-svn: 77736

Also, change scale value to always be 1 when unspecified to machine MachineInst
encoding.

llvm-svn: 77728

metadata related, which I'm waiting on to avoid conflicting with Devang.

llvm-svn: 77721

llvm-svn: 77718

MCSection subclasses yet, but this is a step in the right direction.

llvm-svn: 77708

initialize method, which can be called when an MCContext is available.

llvm-svn: 77687

llvm-svn: 77673

 - This is "experimental" code, I am feeling my way around and working out the
   best way to do things (and learning tblgen in the process). Comments welcome,
   but keep in mind this stuff will change radically.

 - This is enough to match "subb" and friends, but not much else. The next step is to
   automatically generate the matchers for individual operands.

llvm-svn: 77657

llvm-svn: 77602

classes. And define its SubRegClassList.

llvm-svn: 77601

llvm-svn: 77584

Optimize some common usage patterns of atomic built-ins __sync_add_and_fetch() and __sync_sub_and_fetch. 

When the return value is not used (i.e. only care about the value in the memory), x86 does not have to use add to implement these. Instead, it can use add, sub, inc, dec instructions with the "lock" prefix.

This is currently implemented using a bit of instruction selection trick. The issue is the target independent pattern produces one output and a chain and we want to map it into one that just output a chain. The current trick is to select it into a merge_values with the first definition being an implicit_def. The proper solution is to add new ISD opcodes for the no-output variant. DAG combiner can then transform the node before it gets to target node selection.

Problem #2 is we are adding a whole bunch of x86 atomic instructions when in fact these instructions are identical to the non-lock versions. We need a way to add target specific information to target nodes and have this information carried over to machine instructions. Asm printer (or JIT) can use this information to add the "lock" prefix.

llvm-svn: 77582

due to x86 encoding restrictions. This is currently off by default
because it may cause code quality regressions. This is for PR4572.

llvm-svn: 77565

llvm-svn: 77558

llvm-svn: 77553

   and convert code to using it, instead of having lots of things
   poke the isLookupPtrRegClass() method directly.

2. Make PointerLikeRegClass contain a 'kind' int, and store it in
   the existing regclass field of TargetOperandInfo when the
   isLookupPtrRegClass() predicate is set.  Make getRegClass pass
   this into TargetRegisterInfo::getPointerRegClass(), allowing
   targets to have multiple ptr_rc things.

llvm-svn: 77504

support multiple different pointer register classes.

llvm-svn: 77501

llvm-svn: 77480

llvm-svn: 77442

llvm-svn: 77441

llvm-svn: 77438

No functionality change.

llvm-svn: 77432