llvm-svn: 150899

Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication.

llvm-svn: 150873

llvm-svn: 150610

llvm-svn: 150304

This requires some gymnastics to make it available for C code. Remove the names
from the disassembler tables, making them relocation free.

llvm-svn: 150303

Put instruction names into an indexed string table on the side, removing a pointer from MCInstrDesc.

Make them accessible through MCInstrInfo. They are only used for debugging purposes so this doesn't
have an impact on performance. X86MCTargetDesc.o goes from 630K to 461K on x86_64.

llvm-svn: 150245

Store just the SimpleValueType in the generated VT tables for each register class, eliminating static ctors.

llvm-svn: 150173

No change on i386.

llvm-svn: 150170

Teach the MC and disassembler about SoftFail, and hook it up to UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage.

llvm-svn: 150169

llvm-svn: 150167

Flatten some of the arrays in the X86 disassembler tables to reduce space needed to store pointers on 64-bit hosts and reduce relocations needed at startup. Part of PR11953.

llvm-svn: 150161

 X86GenRegisterInfo.inc | 1032 -------------------------------------------------
  1 file changed, 1032 deletions(-)

llvm-svn: 150080

llvm-svn: 150076

1. Added a status note when a config file is loaded directly with load_config. This helps notice loads of lit.cfg from lit.site.cfg
2. Added a status note on the result of a config load. Previously, it was just notifying that it tries to load a config file. Now it will also say whether the load succeeded or the file wasn't found

The two changes give better visibility into which config files were actually loaded by lit. The effect is only on --debug runs.

Patch by Eli Bendersky!

llvm-svn: 149932

llvm-svn: 149814

When adding the {-1, -1} entry to the DFAStateInputTable, we
need to increment the index used to populate the DFAStateEntryTable.
Otherwise, the entry table will be off by one for each transition
after the {-1, -1} entry. PR11908.

llvm-svn: 149713

that just uses the new toolchain probing logic. This fixes linking with -m32 on
64 bit systems (the /32 dir was not being added to the search).

llvm-svn: 149651

It is simpler to define a composite index directly:

  def ssub_2 : SubRegIndex<[dsub_1, ssub_0]>;
  def ssub_3 : SubRegIndex<[dsub_1, ssub_1]>;

Than specifying the composite indices on each register:

  CompositeIndices = [(ssub_2 dsub_1, ssub_0),
                      (ssub_3 dsub_1, ssub_1)] in ...

This also makes it clear that SubRegIndex composition is supposed to be
unique.

llvm-svn: 149556

The final tie breaker comparison also needs to return +/-1, or 0.
This is not a less() function.

This could cause otherwise identical super-classes to be ordered
unstably, depending on what the system qsort routine does with a bad
compare function.

llvm-svn: 149549

It's only by luck that we haven't produced any yet, and clang refuses to
compile them.

llvm-svn: 149546

It was wrong and completely unused.

llvm-svn: 149433

Each SubRegIndex keeps track of how it composes.

llvm-svn: 149423

This class is used to represent SubRegIndex instances instead of the raw
Record pointers that were used before.

No functional change intended.

llvm-svn: 149418

Move to a model where we build whatever branches are checked out
in the source directories.  This was a bit too smart (and complicated)
in handling details best left to the user and the revision control
system.

In addition, get rid of support for llvm-gcc and building gcc as
these are no longer necessary.

llvm-svn: 149149

Patch by Liang Wang!

llvm-svn: 149085

llvm-svn: 148856

Widen the instruction encoder that TblGen emits to a 64 bits, which should accomodate every target I can think of offhand.

llvm-svn: 148833

This will interleave the elements from two or more lists.

llvm-svn: 148824

Unfortunately I don't think there's a fix for this that will work upstream and
also satisfy Clang's -Wunreachable-code, which is a pity. But I'll give it some
more thought -perhaps there's some way out.

llvm-svn: 148645

This will ensure LLVM and Clang build -Wswitch-enum-redundant-default (an on-by-default warning I'm about to add to Clang).

llvm-svn: 148639

Problem: LLVM needs more function attributes than currently available (32 bits).
One such proposed attribute is "address_safety", which shows that a function is being checked for address safety (by AddressSanitizer, SAFECode, etc).

Solution:
- extend the Attributes from 32 bits to 64-bits
- wrap the object into a class so that unsigned is never erroneously used instead
- change "unsigned" to "Attributes" throughout the code, including one place in clang.
- the class has no "operator uint64 ()", but it has "uint64_t Raw() " to support packing/unpacking.
- the class has "safe operator bool()" to support the common idiom:  if (Attributes attr = getAttrs()) useAttrs(attr);
- The CTOR from uint64_t is marked explicit, so I had to add a few explicit CTOR calls
- Add the new attribute "address_safety". Doing it in the same commit to check that attributes beyond first 32 bits actually work.
- Some of the functions from the Attribute namespace are worth moving inside the class, but I'd prefer to have it as a separate commit.

Tested:
"make check" on Linux (32-bit and 64-bit) and Mac (10.6)
built/run spec CPU 2006 on Linux with clang -O2.


This change will break clang build in lib/CodeGen/CGCall.cpp.
The following patch will fix it.

llvm-svn: 148553

When set, this bit indicates that a register is completely defined by
the value of its sub-registers.

Use the CoveredBySubRegs property to infer which super-registers are
call-preserved given a list of callee-saved registers.  For example, the
ARM registers D8-D15 are callee-saved.  This now automatically implies
that Q4-Q7 are call-preserved.

Conversely, Win64 callees save XMM6-XMM15, but the corresponding
YMM6-YMM15 registers are not call-preserved because they are not fully
defined by their sub-registers.

llvm-svn: 148363

paths.

llvm-svn: 148362

Targets can now add CalleeSavedRegs defs to their *CallingConv.td file.
TableGen will use this to create a *_SaveList array suitable for
returning from getCalleeSavedRegs() as well as a *_RegMask bit mask
suitable for returning from getCallPreservedMask().

llvm-svn: 148346

llvm-svn: 148316

This lets lldb give sane output for SmallVectors, e.g.
Before:
(lldb) p sv
(llvm::SmallVector<int, 10>) $0 = {
  (llvm::SmallVectorImpl<int>) llvm::SmallVectorImpl<int> = {
    (llvm::SmallVectorTemplateBase<int>) llvm::SmallVectorTemplateBase<int> = {
      (llvm::SmallVectorTemplateCommon<int>) llvm::SmallVectorTemplateCommon<int> = {
        (llvm::SmallVectorBase) llvm::SmallVectorBase = {
          (void *) BeginX = 0x00007fff5fbff960
...
}

After:
(lldb) p sv
(llvm::SmallVector<int, 10>) $0 = {
  (int) [0] = 42
  (int) [1] = 23
...
}

The script is still a bit rough so expect crashes for vectors of complex types.
Synthetic children are _not_ available in xcode 4.2, newer LLDBs should work though.

llvm-svn: 148308

llvm-svn: 148293

llvm-svn: 148284

Removing unused default switch cases in switches over enums that already account for all enumeration values explicitly.

(This time I believe I've checked all the -Wreturn-type warnings from GCC & added the couple of llvm_unreachables necessary to silence them. If I've missed any, I'll happily fix them as soon as I know about them)

llvm-svn: 148262

llvm-svn: 148147