isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.

llvm-svn: 56189

llvm-svn: 55012

With this patch, all of MultiSource/Applications and all of SPEC2000/2006 pass with
the SimpleSpiller and this fast-path enabled.

llvm-svn: 55000

llvm-svn: 54958

  1) Assign stack slots to new temporaries.
  2) Don't insert an interval into the return vector more than once.

llvm-svn: 54956

  1) Remove an incorrect assertion.
  2) Set the stack slot weight properly.
  3) Resize the VirtRegMap when needed.

llvm-svn: 54949

llvm-svn: 54939

llvm-svn: 54930

Resurrect some ancient code to add spill ranges without attempting folding, remat, or splitting.  This code has been updated to current APIs
in so far as it compiles and, in theory, works, but does not take advantage of recent advancements.  For instance, it could be improved by using
MachineRegisterInfo::use_iterator.

llvm-svn: 54924

llvm-svn: 54766

llvm-svn: 54765

Make the allocation of LiveIntervals explicit, rather than holding them in the r2iMap_ by value.  This will prevent references to them from being invalidated
if the map is changed.

llvm-svn: 54763

llvm-svn: 54425

llvm-svn: 54420

llvm-svn: 54218

llvm-svn: 54186

llvm-svn: 54173

a new ilist_node class, and remove them. Unlike alist_node,
ilist_node doesn't attempt to manage storage itself, so it avoids
the associated problems, including being opaque in gdb.

Adjust the Recycler class so that it doesn't depend on alist_node.
Also, change it to use explicit Size and Align parameters, allowing
it to work when the largest-sized node doesn't have the greatest
alignment requirement.

Change MachineInstr's MachineMemOperand list from a pool-backed
alist to a std::list for now.

llvm-svn: 54146

llvm-svn: 54136

llvm-svn: 54072

Special cases are needed in renumbering when dealing with renumbering after a PHI has been removed.  The interval previously defined
by the PHI needs to be extended to the beginning of its basic block, and the intervals that were inputs need to be trimmed to the end 
of their basic blocks.

llvm-svn: 54070

llvm-svn: 54061

This is tricky business, and will probably take a few more iterations to get
the last kinks out of it.

llvm-svn: 54043

regressions, such as PR2595. Also, there is a significant code-quality
issue in SPEC 464.h264ref and a few others.

llvm-svn: 54014

and knowledge of PseudoSourceValues. This unfortunately isn't sufficient to allow
constants to be rematerialized in PIC mode -- the extra indirection is a
complication.

llvm-svn: 54000

llvm-svn: 53961

to multiply the instruction count by a constant factor in a few places, which
caused the register allocator to require many more iterations.

llvm-svn: 53959

live intervals itself to use an instruction count approximation that is 
not affected by inserting empty indices.

llvm-svn: 53937

llvm-svn: 53779

Fix a leak that this turned up in LowerSubregs.cpp.
And, comment a leak in LiveIntervalAnalysis.cpp.

llvm-svn: 53746

llvm-svn: 53504

Fix PR2536: a nasty spiller bug. If a two-address instruction uses a register but the use portion of its live range is not part of its liveinterval, it must be defined by an implicit_def. In that case, do not spill the use. e.g.
8   %reg1024<def> = IMPLICIT_DEF
12  %reg1024<def> = INSERT_SUBREG %reg1024<kill>, %reg1025, 2

The live range [12, 14) are not part of the r1024 live interval since it's defined by an implicit def. It will not conflicts with live interval of r1025. Now suppose both registers are spilled, you can easily see a situation where both registers are reloaded before the INSERT_SUBREG and both target registers that would overlap.

llvm-svn: 53503

- Change the horrible N^2 isRegReDefinedByTwoAddr. Now callers must supply the operand index of def machineoperand and at most one full scan of non-implicit operands is needed.
- Change local register allocator to use the new isRegReDefinedByTwoAddr instead of reinventing the wheel.

llvm-svn: 53394

MachineMemOperands. The pools are owned by MachineFunctions.

This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.

llvm-svn: 53212

- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc.
- Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list.

llvm-svn: 53097

Remember which MachineOperand we were processing, so we don't have to scan the list to find it again later.
This speeds up live intervals from 0.37s to 0.30s on instcombine.

llvm-svn: 52745

llvm-svn: 52572

llvm-svn: 52485

llvm-svn: 52477

add new instructions.

llvm-svn: 52475