in some more places.

llvm-svn: 99366

to maintain a list of types (one for each result of
the node) instead of a single type.  There are liberal
hacks added to emulate the old behavior in various
situations, but they can start disolving now.

llvm-svn: 98999

llvm-svn: 98904

changing the primary datastructure from being a 
"std::vector<unsigned char>" to being a new TypeSet class
that actually has (gasp) invariants!

This changes more things than I remember, but one major
innovation here is that it enforces that named input 
values agree in type with their output values.

This also eliminates code that transparently assumes (in 
some cases) that SDNodeXForm input/output types are the
same, because this is wrong in many case.

This also eliminates a bug which caused a lot of ambiguous
patterns to go undetected, where a register class would
sometimes pick the first possible type, causing an
ambiguous pattern to get arbitrary results.

With all the recent target changes, this causes no 
functionality change!

llvm-svn: 98534

uses several kinds of opcode values which are not declared within
that enum. This fixes PR5946.

llvm-svn: 92794

icc (#177, partial).  Patch by Erick Tryzelaar.

llvm-svn: 81106

the latter is capable of representing either a primitive or an extended type.

llvm-svn: 78713

llvm-svn: 78610

 - Sorry, I can't help myself.

 - No intended functionality change.

llvm-svn: 74742

operand is the last in a pattern.  There is no
reason this should be true (although apparently
it always is right now).

llvm-svn: 72232

Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead.

llvm-svn: 62762

This will allow predicates to be composed, which will allow the
predicate definitions to become less redundant, and eventually
will allow DAGISelEmitter.cpp to emit less redundant code.

llvm-svn: 57562

they'll be a little more visible. Also, update and reword them a bit.

llvm-svn: 56877

Correctly handle physical register inputs. They are not explicit input operands in the resulting machine instrs.

llvm-svn: 55893

llvm-svn: 55876

def : Pat<(i8 (trunc GR32:$src)),
          (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src), x86_subreg_8bit))>

llvm-svn: 55875

Let tblgen only generate fastisel routines, not the class definition. This makes it easier for targets to define its own fastisel class.

llvm-svn: 55679

llvm-svn: 55545

llvm-svn: 55512

Add support for fast-isel of opcodes that require use of extract_subreg.  Because of how extract_subreg is treated, it requires special case handling.

llvm-svn: 55480

llvm-svn: 55418

llvm-svn: 55401

put each major step in a separate function. This makes the high
level sequence of events easier to follow.

llvm-svn: 55385

have a return type that differs from the operand types.

llvm-svn: 55376

Throw the switch to allow FastISel to emit instructions whose return types different from their inputs.  Next step: adding lowering pattens in FastISel that actually use these newly available opcodes.

llvm-svn: 55349

Enhance TableGen to emit code for FastISel of opcodes with variadic return types without slowing down opcodes that are not variadic.  No such opcodes are currently generated, but in theory it should be a matter of just hitting the switch.

llvm-svn: 55347

Add a RetVT parameter to emitted FastISel methods, so that we will be able to pass the desired return
type down.  This is not currently used.

llvm-svn: 55345

Deepen the map structure tablegen uses to compute FastISel patterns, in preparation for having patterns
with return types that differ from their input types.  This is not yet used.

llvm-svn: 55344

bitcast of constants in fast isel.

llvm-svn: 55325

llvm-svn: 55157

and use it in FastISelEmitter.cpp, and make FastISel
subtarget aware. Among other things, this lets it work
properly on x86 targets that don't have SSE, where it
successfully selects x87 instructions.

llvm-svn: 55156

llvm-svn: 55099

llvm-svn: 55096

llvm-svn: 55093

llvm-svn: 55080

namespace out of the isel emitters and into common code.

llvm-svn: 55079

class hold a MachineRegisterInfo member, and make the
MachineBasicBlock be passed in to SelectInstructions rather
than the FastISel constructor.

llvm-svn: 55076

register class.

llvm-svn: 55008

helper function.

llvm-svn: 55007

llvm-svn: 55004