with subreg - superreg mapping and also fix PR4965.

llvm-svn: 81657

sse, this code falls back to SelectionDAG isel which uses an x87
instruction, which is fine, but not what this test is testing for.

llvm-svn: 81656

llvm-svn: 81546

llvm-svn: 81545

input filename so that opt doesn't print the input filename in the
output so that grep lines in the tests don't unintentionally match
strings in the input filename.

llvm-svn: 81537

llvm-svn: 81532

Follow up to 81494. When the folded reload is narrowed to a 32-bit load then change the destination register to a 32-bit one or add a sub-register index.

llvm-svn: 81496

It's not legal to fold a load from a narrower stack slot into a wider instruction. If done, the instruction does a 64-bit load and that's not
safe. This can happen we a subreg_to_reg 0 has been coalesced. One
exception is when the instruction that folds the load is a move, then we
can simply turn it into a 32-bit load from the stack slot.                                                                                                                    

rdar://7170444

llvm-svn: 81494

isn't legal.

llvm-svn: 81492

post-decrement load/store.

llvm-svn: 81464

llvm-svn: 81415

See the bug report for details.

llvm-svn: 81397

llvm-svn: 81343

llvm-svn: 81327

to be temporarily disabled.

llvm-svn: 81320

printing stuff are quoting symbols now, breaking objc testcases.

llvm-svn: 81319

llvm-svn: 81318

expect the slight syntax differences in the generated code.

llvm-svn: 81305

llvm-svn: 81298

llvm-svn: 81297

llvm-svn: 81293

llvm-svn: 81290

llvm-svn: 81289

could look at this: the top undefined bits of an immediate shouldn't affect
isel (cmp vs cmp.w)

llvm-svn: 81288

llvm-svn: 81285

llvm-svn: 81273

llvm-svn: 81267

to instructions instead of zero extended ones.  This makes the asmprinter
print signed values more consistently.  This apparently only really affects
the X86 backend.

llvm-svn: 81265

llvm-svn: 81262

llvm-svn: 81259

llvm-svn: 81257

of using llvm-as, now that opt supports this.

llvm-svn: 81226

makes the code faster.

llvm-svn: 81220

llvm-svn: 81205

When remat'ing and destination virtual register has a sub-register index. Make sure the sub-register class matches the register class of the remat'ed instruction definition register class.

llvm-svn: 81204

llvm-svn: 81200

depth first order, so it wouldn't process unreachable blocks.
When compiling at -O0, late dead block elimination isn't done
and the bad instructions got to isel.

llvm-svn: 81187

null in the case of an empty struct, so don't try to call getNumValues
on it.

llvm-svn: 81180

from floating-point to integer first, and bitcast the result
back to floating-point. Previously, this test was passing by
falling back to SelectionDAG lowering. The resulting code isn't
as nice, but it's correct and CodeGen now stays on the fast path.

llvm-svn: 81171

llvm-svn: 81084