llvm-svn: 118999

llvm-svn: 118998

future to separate out the ia, ib, da, db variants of the load/store multiple
instructions.

llvm-svn: 118995

parts. Represent the operation mode as an optional operand instead.
rdar://8614429

llvm-svn: 118137

codegen using the patterns; the latter gates the assembler recognizing the
instruction.

llvm-svn: 117931

various X86 and ARM instructions that are bitten by this as isCodeGenOnly,
as they are.

llvm-svn: 117884

and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.

llvm-svn: 117861

got a dulicated line).

llvm-svn: 117860

llvm-svn: 117859

Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the 
instruction 'isCodeGenOnly'.

Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are 
doing this.

llvm-svn: 117858

llvm-svn: 115845

  allow target to correctly compute latency for cases where static scheduling
  itineraries isn't sufficient. e.g. variable_ops instructions such as
  ARM::ldm.
  This also allows target without scheduling itineraries to compute operand
  latencies. e.g. X86 can return (approximated) latencies for high latency
  instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
  e.g. ldm and those used by store multiple instructions, e.g. stm.

llvm-svn: 115755

llvm-svn: 115373

llvm-svn: 115193

llvm-svn: 115160

Now that the MC lowering handles the expansion of the pseudos, kill the horrible
blobs of text.

llvm-svn: 115130

1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones.
2. Cortex-a9 is out-of-order so model all read cycles as cycle 1.
3. Lots of other random fixes for A8 and A9.

llvm-svn: 115121

llvm-svn: 115010

Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub.

llvm-svn: 115008

reflection, this isn't going to achieve the purpose I intended it for.  Back to the drawing board!

llvm-svn: 114710

llvm-svn: 114703

(yet) recognize the 'trap' mnemonic, so we use .short/.long to emit the
opcode directly. On Darwin, however, we do want the mnemonic for more
readable assembly code and better disassembly.

Adjust the .td file to use the 'trap' mnemonic and handle using the binutils
workaround in the assembly printer. Also tweak the formatting of the opcode
values to make them consistent between the MC printer and the old printer.

llvm-svn: 114679

llvm-svn: 113867

llvm-svn: 113849

instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.

This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.

llvm-svn: 113513

llvm-svn: 113289

Make ARM add rN, sp, #imm instructions rematerializable. That's how the address of locals is calculated, so this should
help relieve register pressure a bit. Recalculating the local address is
almost always going to be better than spilling.

llvm-svn: 112503

llvm-svn: 110710

the jtblock_operand print methods.  This avoids extra newlines in the
disassembler's output.  PR7757.

llvm-svn: 109948

being moved around away from the jump table it references. rdar://8104340

llvm-svn: 106483

llvm-svn: 105350

llvm-svn: 104974

make sure accesses to set up the jmpbuf don't get moved after it by the scheduler. Add a missing \n.

llvm-svn: 104967

an alloca() or an llvm.stackrestore(). rdar://8031573

llvm-svn: 104900

llvm-svn: 104661

Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.

llvm-svn: 104419

t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM.

llvm-svn: 104115

Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects.

llvm-svn: 104111

Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM.

llvm-svn: 104102

Obvious in retrospect but not fun to debug.

llvm-svn: 103969