When generating selection tables for Pat instances, TableGen relied on
an output Instruction's Pattern field being set to infer whether a
chain should be added.

This patch adds additional logic to check various flag fields so that
correct code can be generated even if Pattern is unset.

llvm-svn: 159217

"Invalid operand" may be a completely correct diagnostic, but it's often
insufficiently specific to really help identify and fix the problem in
assembly source. Allow a target to specify a more-specific diagnostic kind
for each AsmOperandClass derived definition and use that to provide
more detailed diagnostics when an operant of that class resulted in a
match failure.

rdar://8987109

llvm-svn: 159050

Original commit message:
    Allow up to 64 functional units per processor itinerary.

    This patch changes the type used to hold the FU bitset from unsigned to uint64_t.
    This will be needed for some upcoming PowerPC itineraries.

llvm-svn: 159027

This makes it explicit when ScoreboardHazardRecognizer will be used.
"GenericItineraries" would only make sense if it contained real
itinerary values and still required ScoreboardHazardRecognizer.

llvm-svn: 158963

This patch changes the type used to hold the FU bitset from unsigned to uint64_t.
This will be needed for some upcoming PowerPC itineraries.

llvm-svn: 158679

When returning a 'cannot match due to missing CPU features' error code,
if there are multiple potential matches with different feature sets,
return the smallest set of missing features from the alternatives as
that's most likely to be the one that's desired.

llvm-svn: 158673

There is otherwise not a newline between the CPU name and the start of the next
pass's output which makes both difficult to read.

llvm-svn: 158350

The TableGenBackend base class doesn't do much, and will be removed
completely soon.

Patch by Sean Silva!

llvm-svn: 158311

This fixes an accidental dependence on static initialization order that I introduced yesterday.

Thank you Lang!!!

llvm-svn: 158215

Teach the AsmMatcherEmitter to allow InstAlias' where the suboperands of a complex operand are called out explicitly in the asm string.

llvm-svn: 158183

LLVM is now -Wunused-private-field clean except for
- lib/MC/MCDisassembler/Disassembler.h. Not sure why it keeps all those unaccessible fields.
- gtest.

llvm-svn: 158096

There are some that I didn't remove this round because they looked like
obvious stubs. There are dead variables in gtest too, they should be
fixed upstream.

llvm-svn: 158090

This allows a subtarget to explicitly specify the issue width and
other properties without providing pipeline stage details for every
instruction.

llvm-svn: 157979

llvm-svn: 157885

llvm-svn: 157756

Each register unit has one or two root registers. The full set of
registers containing a given register unit can be computed as the union
of the root registers and their super-registers.

Provide an MCRegUnitRootIterator class to enumerate the roots.

llvm-svn: 157753

It seems I broke C++11.

llvm-svn: 157711

llvm-svn: 157684

Register units are already used internally in TableGen to compute
register pressure sets and overlapping registers. This patch makes them
available to the code generators.

The register unit lists are differentially encoded so they can be reused
for many related registers. This keeps the total size of the lists below
200 bytes for most targets. ARM has the largest table at 560 bytes.

Add an MCRegUnitIterator for traversing the register unit lists. It
provides an abstract interface so the representation can be changed in
the future without changing all clients.

llvm-svn: 157650

Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions.

This required light surgery on the assembler and disassembler
because the instructions use an uncommon encoding. They are
the only two instructions in x86 that use register operands
and two immediates.

llvm-svn: 157634

llvm-svn: 157556

llvm-svn: 157551

making it stronger and more sane.

Delete the code from tblgen that produced the old code.

Besides being a path forward in intrinsic sanity, this also eliminates a bunch of
machine generated code that was compiled into Function.o

llvm-svn: 157545

llvm-svn: 157540

it is (at the cost of 45 bytes of extra table space) so that the verifier can
start using it.

llvm-svn: 157536

llvm-svn: 157523

Store (debugging) register names as offsets into a string table instead
of as char pointers.

llvm-svn: 157449

llvm-svn: 157416

llvm-svn: 157320

case.

llvm-svn: 157312

CodeGenRegisterClass has two constructors. Both need to compute the
TopoSigs BitVector.

llvm-svn: 157271

llvm-svn: 157218

separate side table, using the handy SequenceToOffsetTable class.  This encodes all
these weird things into another 256 bytes, allowing all intrinsics to be encoded this way.

llvm-svn: 156995

are only rejected because they can't be encoded into a 32-bit unit, not because
they contain an unencodable feature.

llvm-svn: 156978

intrinsics that use passed-in arguments.

llvm-svn: 156977

compatibility with LLVM 2.x bitcode files.

llvm-svn: 156976

llvm-svn: 156975

llvm-svn: 156973

TableGen already computes register units as the basic unit of
interference. We can use that to compute the set of overlapping
registers.

This means that we can easily compute overlap sets for one register at a
time. There is no benefit to computing all registers at once.

llvm-svn: 156960

generated code (for Intrinsic::getType) into a table.  This handles common cases right now,
but I plan to extend it to handle all cases and merge in type verification logic as well
in follow-on patches.

llvm-svn: 156905