Simplify array bound checks and clarify comments.  One element array can have same non-zero number as lower bound as well as upper bound.

llvm-svn: 129170

can be used even when main() isn't present in the Module, but it means that you
don't get to read argv[].

llvm-svn: 129163

llvm-svn: 129160

If lower bound is more then upper bound then consider it is an unbounded array.
An array is unbounded if non-zero lower bound is same as upper bound.
If lower bound and upper bound are zero than array has one element.

llvm-svn: 129156

Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap is lowered into a call to the specified trap function at sdisel time.

llvm-svn: 129152

llvm-svn: 129149

llvm-svn: 129148

PR9650
rdar://problem/9257565

llvm-svn: 129147

PR9648
rdar://problem/9257634

llvm-svn: 129146

The previous cleanup of LDRD got overzealous and removed it, causing post-RA
scheduling to get overzealous in breaking antidependencies and invalidate these instructions. Hilarity and invalid assembly ensued.

rdar://9244161

llvm-svn: 129144

Teach 32-bit section loading to use the Memory Manager interface, just like
the 64-bit loading does. Tidy up a few other things here and there.

llvm-svn: 129138

of { i32, void ()* }. Teach the verifier to verify that, deleting copies of
checks strewn about.

llvm-svn: 129128

Add more test cases to exercise the logical branches related to the above change.

llvm-svn: 129117

When two section names share a suffix, reuse the entry in shstrtab.

llvm-svn: 129115

llvm-svn: 129114

with the newer, cleaner model. It uses the IAPrinter class to hold the
information that is needed to match an instruction with its alias. This also
takes into account the available features of the platform.

There is one bit of ugliness. The way the logic determines if a pattern is
unique is O(N**2), which is gross. But in reality, the number of items it's
checking against isn't large. So while it's N**2, it shouldn't be a massive time
sink.

llvm-svn: 129110

llvm-svn: 129107

Patch by Roman Divacky.
Fixes PR9361.

llvm-svn: 129106

llvm-svn: 129105

llvm-svn: 129104

llvm-svn: 129101

induction variable. The preRA scheduler is unaware of induction vars,
so we look for potential "virtual register cycles" instead.

Fixes <rdar://problem/8946719> Bad scheduling prevents coalescing

llvm-svn: 129100

llvm-svn: 129099

Add some test cases.

llvm-svn: 129098

llvm-svn: 129096

PHI values may be deleted, causing the flags to be wrong. This fixes PR9616.

llvm-svn: 129092

And two test cases.

llvm-svn: 129090

llvm-svn: 129087

llvm-svn: 129081

llvm-svn: 129080

llvm-svn: 129079

llvm-svn: 129078

Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector type (vectors of size 3). Also included test cases.

llvm-svn: 129074

tokenization to crash and burn.

llvm-svn: 129051

rdar://problem/9246844

llvm-svn: 129050

is equivalent to any other relevant value; it isn't true in general.
If it is equivalent, the LoopPromoter will tell the AST the equivalence.
Also, delete the PreheaderLoad if it is unused.

Chris, since you were the last one to make major changes here, can you check
that this is sane?

llvm-svn: 129049

The ARM disassembler was not recognizing USADA8 instruction.  Need to add checking for register values
for USAD8 and USADA8.

rdar://problem/9247060

llvm-svn: 129047

llvm-svn: 129045

llvm-svn: 129044

rdar://problem/9246650

llvm-svn: 129042